Simultaneous multithreading: A platform for next-generation processors

IEEE Micro

Volumn 17, Issue 5, 1997, Pages 12-19

  Eggers, Susan J ^a,d,e,k   Emer, Joel S ^b,e,f   Levy, Henry M ^a,e   Lo, Jack L ^a,g   Stamm, Rebecca L ^b,e,h,i   Tullsen, Dean M ^a,c,j  

^a UNIVERSITY OF WASHINGTON   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e IEEE

^f UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^g STANFORD UNIVERSITY   (United States)

^h MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

ⁱ Swathmore College   (United States)

^j ACM

^k University of Washington   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MULTIPROGRAMMING; SHIFT REGISTERS; SURFACE MOUNT TECHNOLOGY;

INSTRUCTION LEVEL PARALLELISM; SIMULTANEOUS MULTITHREADING; THREAD LEVEL PARALLELISM;

MICROPROCESSOR CHIPS;

EID: 0031237789     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.621209     Document Type: Article

References (8)

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3. S. Palacharla, N.P. Jouppi, and J.E. Smith, "Complexity-Effective Superscalar Processors," Proc. Int'l Symp. Computer Architecture, ACM, 1997, pp. 206-218.
4. D. M. Tullsen et al., "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor," Proc. Int'l Symp. Computer Architecture, ACM, 1996, pp. 191-202.
5. S. McFarling, "Combining Branch Predictors," Tech. Report TN-36, Western Research Laboratory, Digital Equipment Corp., Palo Alto, Calif., June 1993.
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7. P.G. Lowney et al., "The Multiflow Trace Scheduling Compiler," J. Supercomputing, May 1993, pp. 51-142.
8. J.L. Lo et al., "Converting Thread-level Parallelism to Instruction-level Parallelism via Simultaneous Multithreading," ACM Trans. Computer Systems, ACM, Aug. 1997.