Optimizing dual-core execution for power efficiency and transient-fault recovery

IEEE Transactions on Parallel and Distributed Systems

Volumn 18, Issue 8, 2007, Pages 1080-1093

  Ma, Yi ^a   Gao, Hongliang ^a   Dimitrov, Martin ^a   Zhou, Huiyang ^a  

^a University of Central Florida   (United States)

Author keywords

Fault tolerance; Low power design; Multiple data stream architectures

Indexed keywords

COMPUTATIONAL COMPLEXITY; OPTIMIZATION; REDUNDANCY; SUPERVISORY AND EXECUTIVE PROGRAMS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

DUAL-CORE EXECUTION; MULTIPLE DATA STREAM ARCHITECTURES; POWER EFFICIENCY;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 34548234204     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2007.4288106     Document Type: Article

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