Fault-tolerant CMP architecture based on SMT technology

Proceedings - 2nd International Multi-Symposiums on Computer and Computational Sciences, IMSCCS'07

Volumn , Issue , 2007, Pages 425-429

  Ning, Linzhi ^a   Yao, Wenbin ^a   Ni, Jun ^b   Yao, Nianmin ^a  

^a HARBIN ENGINEERING UNIVERSITY   (China)

^b University of Iowa   (United States)

Author keywords

CMP; Fault tolerance; SMT; Thread

Indexed keywords

ENHANCED RECOVERY; FAULT DETECTION; FAULT TOLERANCE; NANOTECHNOLOGY; RELIABILITY; SPEECH TRANSMISSION; SURFACE MOUNT TECHNOLOGY; TECHNOLOGY;

(OTDR) TECHNOLOGY; COMPUTATIONAL SCIENCES; FAULT-TOLERANT; IN ORDER; INTERNATIONAL (CO); SIMULTANEOUS MULTI THREADING (SMT); SINGLE CHIPS; TRANSIENT-FAULT DETECTION;

QUALITY ASSURANCE;

EID: 46449138684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMSCCS.2007.4392637     Document Type: Conference Paper

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