Detailed design and evaluation of redundant multithreading alternatives

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 99-110

  Mukherjee, Shubhendu S ^a   Kontz, Michael ^a   Reinhardt, Steven K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; QUEUEING THEORY; REDUNDANCY; TRANSISTORS; VOLTAGE CONTROL;

CHIP-LEVEL REDUNDANT THREADING (CRT); REDUNDANT MULTITHREADING (RMT); SIMULTANEOUS MULTITHREADED SINGLE-CHIP DEVICES;

MULTIPROCESSING PROGRAMS;

EID: 0036287327     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (31)

1. DIVA: A reliable substrate for deep submicron microarchitecture design
2. Memory dependence prediction using store sets
3. Simultaneous multithreading: Multiplying alpha performance
4. Asim: A performance model framework
5. Incorporating fault tolerance in superscalar processors
6. Low cost concurrent error detection in a VLIW architecture using replicated instructions
7. Concurrent error detection using watchdog processors - A survey
8. The 21364 network architecture
9. Concurrent error detection in ALU's by recomputing with shifted operands
10. Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
11. Cost-effective architectural support for rollback recovery in shared-memory multiprocessors
12. Dual use of superscalar datapath for transient-fault detection and recovery
13. Transient fault detection via simultaneous multithreading
14. Fault detection capabilities of alternating logic
15. AR-SMT: A microarchitectural approach to fault tolerance in microprocessor
16. Dependable adaptive computing systems
17. How to compare the performance of two SMT architectures
18. IBM's S/390 G5 microprocessor design
19. Symbiotic job scheduling for a simultaneous multithreading processor
20. A study of time redundant fault tolerance techniques for high-performance pipelined computers
21. Instruction issue logic for high-performance, interruptible. Multiple functional unit, pipelined computers
22. SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery
23. Slipstream processors: Improving both performance and fault tolerance
24. Simultaneous multithreading: Maximizing on-chip parallelism
25. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
26. Transient fault recovery using simultaneous multithreading
27. Increasing superscalar performance through multistreaming