Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation

IET Computers and Digital Techniques

Volumn 9, Issue 2, 2015, Pages 124-133

  Pouyan, Fatemeh ^a   Azarpeyvand, Ali ^a,b   Safari, Saeed ^a   Fakharie, Sied Mehdi ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

^b UNIVERSITY OF ZANJAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ERRORS; FAULT TOLERANCE; RADIATION HARDENING; REDUNDANCY;

ARCHITECTURAL LEVELS; ARCHITECTURAL VULNERABILITY FACTOR; MODERN MICROPROCESSOR; PERFORMANCE ENHANCEMENTS; RELIABILITY DEGRADATION; RELIABILITY IMPROVEMENT; SENSITIVE STRUCTURE; SIMULTANEOUS MULTITHREADED ARCHITECTURES;

ARCHITECTURE;

EID: 84925247733     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2013.0162     Document Type: Article

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