Mechanisms for bounding vulnerabilities of processor structures

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2007, Pages 506-515

  Soundararajan, Niranjan Kumar ^a   Parashar, Angshuman ^a   Sivasubramaniam, Anand ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Microarchitecture; Redundant threading; Transient faults

Indexed keywords

MICROARCHITECTURE; RELIABILITY BUDGETS; TRANSIENT ERRORS; VULNERABILITY REDUCTION;

COMPUTER ARCHITECTURE; CONSTRAINED OPTIMIZATION; ERROR ANALYSIS; SOFTWARE RELIABILITY;

PROGRAM PROCESSORS;

EID: 35348914300     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1250662.1250725     Document Type: Conference Paper

References (23)

1. G. B. Bell and M. H. Lipasti. Deconstructing commit. In Proceedings of the 4th International Symposium on Performance Analysis of Systems and Software, Austin, Texas, March 2004.
2. D. Burger and T. Austin. The SimpleScalar Toolset, Version 3.0. http://www.simplescalar.com.
3. C. Constantinescu. Trends and Challenges in VLSI Circuit Reliability. IEEE Micro, 23(4): 14-19, July-August 2003.
4. X. Fu, J. Poe, T. Li, and J. A. B. Fortes. Characterizing microarchitecture soft error vulnerability phase behavior. In MASCOTS '06: Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation, pages 147-155, Washington, DC, USA, 2006. IEEE Computer Society.
5. M. A. Gomaa and T. N. Vijaykumar. Opportunistic transient-fault detection. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 172-183, 2005.
6. I. Kim and M. H. Lipasti. Understanding scheduling replay schemes. In HPCA '04: Proceedings of the 10th International Symposium on High Performance Computer Architecture, page 198, Washington, DC, USA, 2004. IEEE Computer Society.
7. X. Li, S. V. Adve, P. Bose, and J. A. Rivers. Softarch: An architecture level tool for modeling and analyzing soft errors. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 496-505, 2005.
8. S. Mukherjee, M. Kontz, and S. Reinhardt. Detailed Design and Evaluation of Redundant Multithreading Alternatives. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 99-110, May 2002.
9. S. Mukherjee, C. Weaver, J. Emer, S. Reinhardt, and T. Austin. A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 29-40, December 2003.
10. S. Palacharla. Complexity-Effective Superscalar Processors. PhD thesis, University of Wisconsin - Madison, 1998.
11. A. Parashar, S. Gurumurthi, and A. Sivasubramaniam. A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 376-386, June 2004.
12. A. Parashar, S. Gurumurthi, and A. Sivasubramaniam. Slick: Slice-based locality exploitation for efficient redundant multithreading. In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.
13. D. Ponomarev, G. Kucuk, and K. Ghose. Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pages 90-101, Washington, DC, USA, 2001. IEEE Computer Society.
14. J. Ray, J. Hoe, and B. Falsafi. Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 214-224, December 2001.
15. V. K. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding prediction-based partial redundant threading for low-overhead, high-coverage fault tolerance. In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.
16. S. Reinhardt and S. Mukherjee. Transient Fault Detection via Simultaneous Multithreading. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 25-36, June 2000.
17. E. Rotenberg. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. In Proceedings of the International Symposium on Fault-Tolerant Computing (FTCS), pages 84-91, June 1999.
18. J. Shen and M. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors (Beta Edition). McGraw Hill, 2003.
19. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically Characterizing Large Scale Program Behavior. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002.
20. P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi. Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2002.
21. K. Sundaramoorthy, Z. Purser, and E. Rotenburg. Slipstream processors: improving both performance and fault tolerance. In ASPLOS-IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, pages 257-268, 2000.
22. T. Vijaykumar, I. Pomeranz, and K. Cheng. Transient-Fault Recovery via Simultaneous Multithreading. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 87-98, May 2002.
23. C. Weaver, J. Emer, S. Mukherjee, and S. Reinhardt. Techniques to Reduce the Soft Error Rate of High-Performance Microprocessor. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 264-275, June 2004.