SCOPUS 정보 검색 플랫폼

Volumn 5, Issue 1, 2006, Pages 22-25

A case for fault tolerance and performance enhancement using chip multi-processors

Author keywords

[No Author keywords available]

Indexed keywords

BACK PROCESSORS; DUAL-CORE EXECUTION (DCE); TRANSIENT FAULTS;

COMPUTER HARDWARE; CONSTRAINT THEORY; FAULT TOLERANCE; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; SUPERVISORY AND EXECUTIVE PROGRAMS;

MULTIPROCESSING SYSTEMS;

EID: 33947313321 PISSN: 15566056 EISSN: None Source Type: Journal
DOI: 10.1109/L-CA.2006.1 Document Type: Article

Times cited : (13)

References (15)

1
- 33947325735
- T. Austin, DIVA: a reliable substrate for deep submicron microarchitecture design, MICRO-32, 1999.
- T. Austin, "DIVA: a reliable substrate for deep submicron microarchitecture design", MICRO-32, 1999.

2
- 84944390453
- Beating in-order stalls with flea-flicker two pass pipelining
- R. Barnes et. al., "Beating in-order stalls with flea-flicker two pass pipelining", MICRO-36, 2003.
- (2003) MICRO-36
- Barnes, R.¹ et., al.²

4
- 33749382060
- Out-of-order commit processors
- A. Cristal el al., "Out-of-order commit processors", HPCA-10, 2004.
- (2004) HPCA-10
- Cristal, A.¹ el al²

5
- 0030662863
- J. Dundas and T. Mudge, "Improving data cache performance by pre-executing instructions under a cache miss", ICS-97, 1997.
- Improving data cache performance by pre-executing instructions under a cache miss , vol.ICS-97 , pp. 1997
- Dundas, J.¹ Mudge, T.²

6
- 0038346239
- M. Gomma et. al., "Transient-fault recovery for chip multiprocessors", ISCA-30, 2003.
- Transient-fault recovery for chip multiprocessors , vol.ISCA-30 , pp. 2003
- Gomma, M.¹ et., al.²

7
- 28444483117
- S. Mukherjee, J. Emer, and S. Reinhardt, "The soft error problem, an architectural perspective", HPCA-11, 2005.
- The soft error problem, an architectural perspective , vol.HPCA-11 , pp. 2005
- Mukherjee, S.¹ Emer, J.² Reinhardt, S.³

8
- 0036287327
- S. Mukherjee, M. Kontz, and S. Reinhardt, "Detailed design and evaluation of redundant multithreading alternatives", ISCA-29, 2002.
- Detailed design and evaluation of redundant multithreading alternatives , vol.ISCA-29 , pp. 2002
- Mukherjee, S.¹ Kontz, M.² Reinhardt, S.³

9
- 84955506994
- O. Mutlu et. al., "Runahead execution; an alternative to very large instruction windows for out-of-order processors", HPCA-9, 2003.
- Runahead execution; an alternative to very large instruction windows for out-of-order processors , vol.HPCA-9 , pp. 2003
- Mutlu, O.¹ et., al.²

10
- 0035691556
- T. Ray, J. Hoe, and B. Falsafi, Dual use of superscalar datapath for transient-fault detection and recovery, MICRO-34, 2001
- T. Ray, J. Hoe, and B. Falsafi, "Dual use of superscalar datapath for transient-fault detection and recovery", MICRO-34, 2001

11
- 0032597692
- E. Rotenbcrg, "AR-SMT: a microarchitectural approach to fault tolerance in microprocessors", FTCS-29, 1999.
- AR-SMT: A microarchitectural approach to fault tolerance in microprocessors , vol.FTCS-29 , pp. 1999
- Rotenbcrg, E.¹

12
- 12844269176
- Continual flow pipelines
- S. T. Srinivasan et. al., "Continual flow pipelines", ASPLOS-11, 2004.
- (2004) ASPLOS-11
- Srinivasan, S.T.¹ et., al.²

13
- 0034441012
- K. Sundaramoorthy et. al., Slipstream processors: improving both performance and fault tolerance, ASPLOS-9, 2000.
- K. Sundaramoorthy et. al., "Slipstream processors: improving both performance and fault tolerance", ASPLOS-9, 2000.

14
- 0036290674
- T. Vijaykumar et. al. "Transient-fault recovery using simultaneous multithreading", ISCA-29, 2002.
- Transient-fault recovery using simultaneous multithreading , vol.ISCA-29 , pp. 2002
- Vijaykumar, T.¹ et., al.²

15
- 33644919336
- H. Zhou, Dual-core execution: building a highly scalable single-thread instruction window, PACT'05, 2005.
- H. Zhou, "Dual-core execution: building a highly scalable single-thread instruction window", PACT'05, 2005.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.