FluidCheck: A redundant threading-based approach for reliable execution in manycore processors

ACM Transactions on Architecture and Code Optimization

Volumn 12, Issue 4, 2015, Pages

  Kalayappan, Rajshekar ^a   Sarangi, Smruti R ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Checker architectures; Redundant multithreading; Reliability

Indexed keywords

COMPLEX NETWORKS; DISTRIBUTED COMPUTER SYSTEMS; ENERGY EFFICIENCY; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; MULTITASKING; NETWORK ARCHITECTURE; PROGRAM PROCESSORS; RADIATION HARDENING; RECONFIGURABLE HARDWARE; RELIABILITY; VLSI CIRCUITS;

ARCHITECTURAL ENHANCEMENT; BAG-OF-TASKS APPLICATIONS; MANY-CORE PROCESSORS; NETWORK-ON-CHIP(NOC); PERFORMANCE PENALTIES; REDUNDANT MULTITHREADING; RELIABLE EXECUTION; SIMULTANEOUS MULTI-THREADING;

NETWORK-ON-CHIP;

EID: 84954315984     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2842620     Document Type: Article

References (36)

1. C. Acosta, F. J. Cazorla, A. Ramirez, and M. Valero. 2009. Thread to core assignment in SMT on-chip multiprocessors. In SBAC-PAD.
2. T. M. Austin. 1999. DIVA: A reliable substrate for deep submicron microarchitecture design. In Micro.
3. D. Bernick, B. Bruckert, P. D. Vigna, D. Garcia, R. Jardine, J. Klecka, and J. Smullen. 2005. Non Stop® advanced architecture. In DSN.
4. S. Chatterjee, C. Weaver, and T. Austin. 2000. Efficient checker processor design. In Micro.
5. A. El-Moursy, R. Garg, D. H. Albonesi, and S. Dwarkadas. 2006. Compatible phase co-scheduling on a CMP of multi-threaded processors. In IPDPS.
6. J. Feliu, J. Sahuquillo, S. Petit, and J. Duato. 2013. L1-bandwidth aware thread allocation in multicore SMT processors. In PACT.
7. M. A. Gomaa and T.N. Vijaykumar. 2005. Opportunistic transient-fault detection. SIGARCH Comput. Archit. News 33, 2 (May 2005), 172-183.
8. W. Huang, K. Rajamani, M. R. Stan, and K. Skadron. 2011. Scaling with design constraints: Predicting the future of big chips. Micro 31, 4 (2011), 16-29.
9. S. Hukerikar, K. Teranishi, P. C. Diniz, and R. F. Lucas. 2014. An evaluation of lazy fault detection based on adaptive redundant multithreading. In HPEC.
10. H. Jeon and M. Annavaram. 2012. Warped-DMR: Light-weight error detection for GPGPU. In MICRO.
11. A. B. Kahng, B. Li, L. Peh, and K. Samadi. 2009. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In DATE.
12. R. Kalayappan and S. R. Sarangi. 2013. A survey of checker architectures. Comput. Surveys 45, 4, Article 48 (Aug. 2013).
13. S. Kumar and A. Aggarwal. 2008. Speculative instruction validation for performance-reliability trade-off. In HPCA.
14. S. Li, J. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Micro.
15. G. Malhotra, P. Aggarwal, A. Sagar, and S. R. Sarangi. 2014. ParTejas: A parallel simulator for multicore processors. In ISPASS.
16. P. Montesinos, W. Liu, and J. Torrellas. 2007. Using register lifetime predictions to protect register files against soft errors. In DSN.
17. S. S. Mukherjee, M. Kontz, and S. K. Reinhardt. 2002. Detailed design and evaluation of redundant multithreading alternatives. SIGARCH Comput. Archit. News 30, 2 (May 2002), 99-110.
18. S. Parekh, S. Eggers, and H. Levy. 2000. Thread-Sensitive Scheduling for SMT Processors. Technical Report. University of Washington.
19. H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi. 2004. Pinpointing representative portions of large intel® Itanium® programs with dynamic instrumentation. In Micro.
20. M. Prvulovic, Z. Zhang, and J. Torrellas. 2002. ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors. In ISCA.
21. M. W. Rashid and M. C. Huang. 2008. Supporting highly-decoupled thread-level redundancy for parallel programs. In HPCA.
22. M. W. Rashid, E. J. Tan, M. C. Huang, and D. H. Albonesi. 2005. Exploiting coarse-grain verification parallelism for power-efficient fault tolerance. PACT (2005).
23. J. Ray, J. C. Hoe, and B. Falsafi. 2001. Dual use of superscalar datapath for transient-fault detection and recovery. In Micro.
24. S. K. Reinhardt and S. S. Mukherjee. 2000. Transient fault detection via simultaneous multithreading. In ISCA.
25. E. Rotenberg. 1999. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In 29th International Symposium on Fault-Tolerant Computing. 84-91.
26. S. R. Sarangi, R. Kalayappan, P. Kallurkar, S. Goel, and E. Peter. 2015. Tejas: A java based versatile microarchitectural simulator. In PATMOS.
27. A. Settle, J. Kihm, A. Janiszewski, and D. Connors. 2004. Architectural support for enhanced SMT job scheduling. In PACT.
28. L. Spainhower and T. A. Gregg. 1999. IBM S/390 parallel enterprise server G5 fault tolerance: A historical perspective. IBM J. Res. Dev. 43, 5.6 (1999), 863-873.
29. P. Subramanyan, V. Singh, K. K. Saluja, and E. Larsson. 2010. Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. In DATE.
30. K. Sundaramoorthy, Z. Purser, and E. Rotenburg. 2000. Slipstream processors: Improving both performance and fault tolerance. In ASPLOS.
31. S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. 2008. CACTI 5.1. Technical Report. HP Laboratories.
32. D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. 1996. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In ACM SIGARCH Comput. Archit. News 24, 2 (May 1996), 191-202.
33. D. M. Tullsen, S. J. Eggers, and H. M. Levy. 1995. Simultaneous multithreading: Maximizing on-chip parallelism. In ISCA.
34. X. Vera, J. Abella, J. Carretero, and A. González. 2009. Selective replication: A lightweight technique for soft errors. ACM Trans. Comput. Syst. 27, 4, Article 8 (Dec. 2009).
35. J. Wadden, A. Lyashevsky, S. Gurumurthi, V. Sridharan, and K. Skadron. 2014. Real-world design and evaluation of compiler-managed GPU redundant multithreading. In ISCA.
36. Huiyang Zhou. 2006. A case for fault tolerance and performance enhancement using chip multi-processors. IEEE Comput. Archit. Lett. 5, 1 (Jan. 2006), 22-25.