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Volumn , Issue , 2010, Pages 1572-1577

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors

Author keywords

[No Author keywords available]

Indexed keywords

CMOS SCALING; COARSE-GRAINED; COMMODITY MARKETS; ENERGY CONSUMPTION; FAULT-TOLERANT; GENERAL PURPOSE PROCESSORS; IN-CHIP; MANUFACTURING DEFECTS; MICRO-PROCESSORS; MULTI-THREADING; PERFORMANCE PENALTIES; PROCESS VARIATION; SINGLE PROCESSORS; TRANSIENT FAULTS;

EID: 77953101372     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (24)

References (28)
  • 4
    • 33846118079 scopus 로고    scopus 로고
    • Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation
    • S. Y. Borkar. Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. IEEE Micro, 25(6), 2005.
    • (2005) IEEE Micro , vol.25 , Issue.6
    • Borkar, S.Y.1
  • 5
    • 36049042981 scopus 로고    scopus 로고
    • Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
    • C. LaFrieda et al. Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. In Proceedings of the 37th DSN, Jun. 2007.
    • Proceedings of the 37th DSN, Jun. 2007
    • LaFrieda, C.1
  • 6
    • 0002532714 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • D. Brooks et al. Wattch: a framework for architectural-level power analysis and optimizations. Proc. of the 27th ISCA, 2000.
    • Proc. of the 27th ISCA, 2000
    • Brooks, D.1
  • 7
    • 84944408150 scopus 로고    scopus 로고
    • Razor: A low-power pipeline based on circuit-level timing speculation
    • D. Ernst et al. Razor: A low-power pipeline based on circuit-level timing speculation. In MICRO 36: Proc. of the 36th MICRO, 2003.
    • MICRO 36: Proc. of the 36th MICRO, 2003
    • Ernst, D.1
  • 10
    • 33749393518 scopus 로고    scopus 로고
    • Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors
    • Meyrem Kyrman et al. Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. In MICRO 38: Proc. of the 38th MICRO, pages 245-256, 2005.
    • (2005) MICRO 38: Proc. of the 38th MICRO , pp. 245-256
    • Kyrman, M.1
  • 12
    • 58149131807 scopus 로고    scopus 로고
    • DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals
    • Jul-Dec.
    • A. Golander, S. Weiss, and R. Ronen. DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Computer Architecture Letters. Jul-Dec. 2008, 7(2).
    • (2008) IEEE Computer Architecture Letters , vol.7 , Issue.2
    • Golander, A.1    Weiss, S.2    Ronen, R.3
  • 15
    • 85008031236 scopus 로고    scopus 로고
    • MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
    • Jan.
    • A. J. KleinOsowski and D. J. Lilja. MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. IEEE Computer Architecture Letters, Jan. 2002.
    • (2002) IEEE Computer Architecture Letters
    • KleinOsowski, A.J.1    Lilja, D.J.2
  • 22
    • 0032597692 scopus 로고    scopus 로고
    • AR-SMT: A Microarchitectural Approach to Fault Tolerance in a Microprocessor
    • E. Rotenberg . AR-SMT: A Microarchitectural Approach to Fault Tolerance in a Microproce ssor. Proceedings of FTCS, 1999.
    • Proceedings of FTCS, 1999
    • Rotenberg, E.1
  • 25
    • 0034443570 scopus 로고    scopus 로고
    • Symbiotic jobscheduling for a simultaneous multithreaded processor
    • Allan Snavely and Dean M. Tullsen. Symbiotic jobscheduling for a simultaneous multithreaded processor. In Proc. of 8th ASPLOS, 2000.
    • Proc. of 8th ASPLOS, 2000
    • Snavely, A.1    Tullsen, D.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.