Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 1572-1577

  Subramy, Pramod ^a   Singh, Virendra ^a   Saluja, Kewal K ^b   Larsson, Erik ^c  

^a INDIAN INSTITUTE OF SCIENCE   (India)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS SCALING; COARSE-GRAINED; COMMODITY MARKETS; ENERGY CONSUMPTION; FAULT-TOLERANT; GENERAL PURPOSE PROCESSORS; IN-CHIP; MANUFACTURING DEFECTS; MICRO-PROCESSORS; MULTI-THREADING; PERFORMANCE PENALTIES; PROCESS VARIATION; SINGLE PROCESSORS; TRANSIENT FAULTS;

FAULT TOLERANCE; MULTIPLEXING; MULTIPROCESSING SYSTEMS; MULTITASKING; REDUNDANCY;

QUALITY ASSURANCE;

EID: 77953101372     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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