Supporting highly-decoupled thread-level redundancy for parallel programs

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2008, Pages 393-404

  Rashid, M Wasiur ^a   Huang, Michael C ^a  

^a University of Rochester

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL SUPPORTS; CIRCUIT ERRORS; CRITICAL CHARGES; CRITICAL PATHS; DESIGN GOALS; DESIGN ISSUES; DEVICE DIMENSIONS; MEMORY SUB SYSTEMS; MICROARCHITECTURE; NOISE TOLERANCES; ON THE FLIES; OPERATING VOLTAGES; PARALLEL CODES; PARALLEL EXECUTIONS; PARALLEL PROGRAMS; PERFORMANCE DEGRADATIONS; PROGRAM EXECUTIONS; THROUGHPUT LOSSES;

CODES (SYMBOLS); COMPUTERS; NETWORKS (CIRCUITS); QUALITY ASSURANCE; REDUNDANCY; RELIABILITY;

COMPUTER ARCHITECTURE;

EID: 57749181987     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658655     Document Type: Conference Paper

References (62)

1. C. Amza et al. TreadMarks: Shared Memory Computing on Networks of Workstations. IEEE Computer, Vol. 29(2):18-28, Feb. 1996.
2. H. Ando et al. A 1.3-GHz Fifth-Generation SPARC64 Microprocessor. IEEE J. Solid-State Circuits, Vol. 38(11):1896-1905, Nov. 2003.
3. T. Austin. DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. In Int. Symp. Microarchitecture. Nov. 1999.
4. D. Bernick et al. NonStop®Advanced Architecture. In Int. Conf. Dependable Systems and Networks. Jun.-Jul. 2005.
5. P. Bernstein. Sequoia: A Fault-tolerant Tightly Coupled Multiprocessor for Transaction Processing. IEEE Computer, Vol. 21(2):37-45, Feb. 1988.
6. A. Bondavalli, S. Chiaradonna, and F. Giandomenico. Efficient Fault Tolerance: An Approach to Deal with Transient Faults in Multiprocessor Architectures. In International Conference on Parallel and Distributed Systems. Dec. 1994.
7. D. Burger and T. Austin. The SimpleScalar Tool Set, Version 2.0. Technical report 1342, Computer Sciences Department, University of Wisconsin-Madison, Jun. 1997.
8. D. Chardonnereau et al. Fault Tolerant 32-bit RISC Processor: Implementation and Radiation test Results. In Single-Event Effects Symposium. Apr. 2002.
9. S. Chatterjee, C. Weaver, and T. Austin. Efficient Checker Processor Design. In Int. Symp. Microarchitecture. Dec. 2000.
10. Cisco Systems. Cisco 12000 Single Event Upset Failures Overview and Work Around Summary, 2003. http://www.cisco.com/warp/public/770/fn25994.shtml.
11. Compaq Computer Corporation. Alpha 21264/EV6 Microprocessor Hardware Reference Manual, Sep. 2000.
12. D. E. Culler and J. P. Singh. Parallel Computer Architecture: a Hardware/Software Approach. Morgan Kaufmann, 1999.
13. T. Dell. A While Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory. IBM Microelectronics Division, Nov. 1997.
14. S. Dwarkadas et al. Parallelization of General Linkage Analysis Problems. Human Heredity, Vol. 44:127-141, 1994.
15. B. Gill et al. An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories. In Design, Automation and Test in Europe. Mar. 2005.
16. B. Gold et al. TRUSS: A Reliable, Scalable Server Architecture. IEEE Micro, Vol. 25(6):51-59, Nov./Dec. 2005.
17. M. Gomaa et al. Transient-Fault Recovery for Chip Multiprocessors. In Int. Symp. Computer Architecture. Jun. 2003.
18. S. Hareland et al. Impact of CMOS Process Scaling and SOI on the Soft Error Rates of Logic Processes. In IEEE Symp. VLSI Technology. Jun. 2001.
19. P. Hazucha et al. Measurements and Analysis of SER-Tolerant Latch in a 90-nm Dual-Vt CMOS Process. IEEE J. Solid-State Circuits, Vol. 39(9):1536-1543, Sep. 2004.
20. R. Kumar et al. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In Int. Symp. Microarchitecture. Dec. 2003.
21. P. Lee, N. Ghani, and K. Heron. A Recovery Cache for the PDP-11. IEEE Transactions on Computers, Vol. 29(6):546-549, Jun. 1980.
22. Y. Lee and K. Shin. Design and Evaluation of a Fault-Tolerant Multiprocessor Using Hardware Recovery Blocks. IEEE Transactions on Computers, Vol. 33(2):113-124, Feb. 1984.
23. L. Longden et al. Designing A Single Board Computer For Space Using The Most Advanced Processor and Mitigation Technologies. In European Space Components Conference, ESCCON 2002. Sep. 2002.
24. D. Lyons. Sun Screen. Forbes, Nov. 2000. http://www.forbes.com/ global/2000/1113/0323026a.html.
25. D. Mavis and P. Eaton. Soft Error Rate Mitigation Techniques for Modern Microcircuits. In Int. Reliability Physics Symp. Apr. 2002.
26. S. Mitra et al. Robust System Design with Build-in Soft-Error Resilience. IEEE Computer, Vol. 38(2):43-52, 2005.
27. S. Mukherjee, M. Kontz, and S. Reinhardt. Detailed Design and Evaluation of Redundant Multithreading Alternatives. In Int. Symp. Computer Architecture. May 2002.
28. S. Narayanasamy, C. Pereira, and B. Calder. Recording Shared Memory Dependencies Using Strata. In Int. Conf. Architectural Support for Programming Languages and Operating Systems. Oct. 2006.
29. J. Neumann. Probabilistic Logics and the Synthesis of Reliable Organisms form Unreliable Components. In C. Shannon and J. McCarthy, editors, Automata Studies, pp. 43-98. Princeton University Press, 1956.
30. M. Nicolaidis. Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies. In IEEE VLSI Test Symp. Apr. 1999.
31. A. Parashar et al. A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. In Int. Symp. Computer Architecture. Jun. 2004.
32. J. Patel and L. Fung. Concurrent Error Detection in Multiply and Divide Arrays. IEEE Transactions on Computers, Vol. 32:417-422, 1983.
33. W. Peterson. On Checking an Adder. IBM Journal of Research and Development, Vol. 2(2):166-168, Apr. 1958.
34. M. Prvulovic, Z. Zhang, and J. Torrellas. ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. In Int. Symp. Computer Architecture. May 2002.
35. M. Rashid et al. Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance. In Int. Conf. Parallel Architectures and Compilation Techniques. Sep. 2005.
36. J. Ray et al. Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery. In Int. Symp. Microarchitecture. Dec. 2001.
37. S. Reinhardt and S. Mukherjee. Transient Fault Detection via Simultaneous Multithreading. In Int. Symp. Computer Architecture. Jun. 2000.
38. J. Rohr. STAREX Self-Repair Routines: Software Recovery in the JPL-STAR Computer. In Int. Symp. Fault-Tolerant Computing. 1973.
39. E. Rotenberg. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. In Int. Symp. Fault-Tolerant Computing. Jun. 1999.
40. S. Rusu et al. A 1.5-Ghz 130-nm Itanium® 2 Processor With 6-MB On-die L3 Cache. IEEE J. Solid-State Circuits, Vol. 38(11):1887-1895, Nov. 2003.
41. N. Seifert et al. Historical Trend in Alpha-Particle induced Soft Error Rates of the Alpha™ Microprocessor. In Int. Reliability Physics Symp. Apr. 2001.
42. P. Shivakuma et al. Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. In Int. Conf. Dependable Systems and Networks. Jun. 2002.
43. B. Sinharoy et al. POWER5 System Microarchitecture. IBM Journal of Research and Development, Vol. 49(4/5):505-521, Sep. 2005.
44. T. Slegel et al. IBM's S/390 G5 Microprocessor Design. IEEE Micro, Vol. 19(2):12-23, Mar./Apr. 1999.
45. J. Smolens et al. Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitecture. In Int. Symp. Microarchitecture. Nov. 2004.
46. J. Smolens et al. Fingerprinting: Bounding the Soft-Error Detection Latency and Bandwidth. In Int. Conf. Architectural Support for Programming Languages and Operating Systems. Oct. 2004.
47. J. Smolens et al. Reunion: Complexity-Effective Multicore Redundancy. In Int. Symp. Microarchitecture. Dec. 2006.
48. D. Sorin et al. SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. In Int. Symp. Computer Architecture. May 2002.
49. L. Spainhower et al. IBM's ES/9000 Model 982's fault-tolerant design for consolidation. IEEE Micro, Vol. 14(3):48-59, Feb. 1994.
50. Y. Tamir and T. Frazier. Application-transparent Process-level Error Recovery for Multicomputers. In Hawaii Int. Conf. System Sciences. Jan. 1989.
51. Y. Tamir, M. Tremblay, and D. Rennels. The Implementation and Application of Micro Rollback in Fault-Tolerant VLSI Systems. In Int. Symp. Fault-Tolerant Computing. Jun. 1988.
52. J. Tendler et al. POWER4 System Microarchitecture. IBM Journal of Research and Development, Vol. 46(1):5-25, Jan. 2002.
53. T. Vijaykumar et al. Transient-Fault Recovery via Simultaneous Multithreading. In Int. Symp. Computer Architecture. May 2002.
54. N. Wang et al. Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. In Int. Conf. Dependable Systems and Networks. Jun. 2004.
55. J. Watterson and J. Hallenbeck. Modulo 3 Residue Checker: New Results on Performance and Cost. IEEE Transactions on Computers, Vol. 37(5):608-612, 1988.
56. C. Weaver et al. Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. In Int. Symp. Computer Architecture. Jun. 2004.
57. S. Woo et al. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Int. Symp. Computer Architecture. Jun. 1995.
58. K. Wu, W. Fuchs, and J. Patel. Error Recovery in Shared Memory Multiprocessors Using Private Caches. IEEE Trans. Parallel and Distributed Systems, Vol. 1(2):231-240, Apr. 1990.
59. M. Xu, R. Bodik, and M. Hill. A "Flight Data Recorder" for Enabling Full-system Multiprocessor Deterministic Replay. In Int. Symp. Computer Architecture. Jun. 2003.
60. M. Xu, R. Bodik, and M. Hill. A Regulated Transitive Reduction (RTR) for Longer Memory Race Recording. In Int. Conf. Architectural Support for Programming Languages and Operating Systems. Oct. 2006.
61. K. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, Vol. 16(2):28-40, Apr. 1996.
62. J. Ziegler and W. Lanford. Effect of Cosmic Rays on Computer Memories. Science, Vol. 206(16):776-788, Nov. 1979.