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Volumn 2006, Issue , 2006, Pages

Compatible phase co-scheduling on a CMP of multi-threaded processors

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; MICROPROCESSOR CHIPS; SCHEDULING; SERVERS; THROUGHPUT;

EID: 33847095957     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639376     Document Type: Conference Paper
Times cited : (51)

References (21)
  • 1
    • 85033333371 scopus 로고    scopus 로고
    • D. Burger and T. Austin. The Simplescalar toolset, version 2.0. Technical Report TR-97-1342, University of Wisconsin-Madison, June 1997
    • D. Burger and T. Austin. The Simplescalar toolset, version 2.0. Technical Report TR-97-1342, University of Wisconsin-Madison, June 1997.
  • 7
    • 0032639289 scopus 로고    scopus 로고
    • The Alpha 21264 Microprocessor
    • March/April
    • R. Kessler. The Alpha 21264 Microprocessor. IEEE Micro, 19(2):24-36, March/April 1999.
    • (1999) IEEE Micro , vol.19 , Issue.2 , pp. 24-36
    • Kessler, R.1
  • 9
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-Way Multithreaded Spare Processor
    • March
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-Way Multithreaded Spare Processor. IEEE Micro, 25(2):21-29, March 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 10
    • 0038633602 scopus 로고    scopus 로고
    • Hyperthreading Technology in the Netburst Microarchitecture
    • March
    • D. Koufaty and D. T. Marr. Hyperthreading Technology in the Netburst Microarchitecture. IEEE Micro, 23(2):56-65, March 2003.
    • (2003) IEEE Micro , vol.23 , Issue.2 , pp. 56-65
    • Koufaty, D.1    Marr, D.T.2
  • 13
    • 20344403770 scopus 로고    scopus 로고
    • Montecito: A Dual-Core, Dual-Thread Itanium Processor
    • March
    • C. McNairy and R. Bhatia. Montecito: A Dual-Core, Dual-Thread Itanium Processor. IEEE Micro, 25(2):10-20, March 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 10-20
    • McNairy, C.1    Bhatia, R.2
  • 15
    • 0013229812 scopus 로고    scopus 로고
    • Thread-Sensitive Scheduling for SMT Processors
    • Technical report, University of Washington
    • S. Parekh, S. Eggers, and H. Levy. Thread-Sensitive Scheduling for SMT Processors. Technical report, University of Washington, 2000.
    • (2000)
    • Parekh, S.1    Eggers, S.2    Levy, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.