L1-bandwidth aware thread allocation in multicore SMT processors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2013, Pages 123-132

  Feliu, Josue ^a   Sahuquillo, Julio ^a   Petit, Salvador ^a   Duato, Jose ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

bandwidth aware scheduling; SMT; thread allocation

Indexed keywords

BANDWIDTH-AWARE; DYNAMIC RESOURCE REQUIREMENTS; KEY ISSUES; NOVEL HARDWARE; PROCESSOR PERFORMANCE; RESOURCE SHARING; SHARED RESOURCES; THREAD ALLOCATION;

SURFACE MOUNT TECHNOLOGY;

PARALLEL ARCHITECTURES;

EID: 84887462279     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2013.6618810     Document Type: Conference Paper

References (25)

1. D. M. Tullsen, S. J. Eggers, and H. M. Levy, "Simultaneous multithreading: maximizing on-chip parallelism," SIGARCH Comput. Archit. News, vol. 23, no. 2, pp. 392-403, May 1995.
2. C. D. Antonopoulos, D. S. Nikolopoulos, and T. S. Papatheodorou, "Realistic workload scheduling policies for taming the memory bandwidth bottleneck of smps," in High Performance Computing (HiPC), 2004, pp. 286-296.
3. D. Xu, C. Wu, and P.-C. Yew, "On mitigating memory bandwidth contention through bandwidth-aware scheduling," in International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010, pp. 237-248.
4. L. Tang, J. Mars, N. Vachharajani, R. Hundt, and M.-L. Soffa, "The impact of memory subsystem resource sharing on datacenter applications," in International Symposium on Computer Architecture (ISCA), 2011, pp. 283-294.
5. S. Zhuravlev, S. Blagodurov, and A. Fedorova, "Addressing shared resource contention in multicore processors via scheduling," in International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2010, pp. 129-142.
6. J. Feliu, J. Sahuquillo, S. Petit, and J. Duato, "Understanding Cache Hierarchy Contention in CMPs to Improve Job Scheduling," in International Parallel Distributed Processing Symposium (IPDPS), 2012, pp. 508-519.
7. R. Knauerhase, P. Brett, B. Hohlt, T. Li, and S. Hahn, "Using os observations to improve performance in multicore systems," IEEE Micro, vol. 28, no. 3, pp. 54-66, may 2008.
8. A. Fedorova, M. Seltzer, and M. D. Smith, "Improving performance isolation on chip multiprocessors via an operating system scheduler," in International Conference on Parallel Architecture and Compilation Techniques (PACT), 2007, pp. 25-38.
9. Y. Jiang, K. Tian, and X. Shen, "Combining locality analysis with online proactive job co-scheduling in chip multiprocessors," in International Conference on High Performance Embedded Architectures and Compilers, (HiPEAC), 2010, pp. 201-215.
10. S. Eyerman and L. Eeckhout, "Probabilistic job symbiosis modeling for smt processor scheduling," in International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2010, pp. 91-102.
11. V. C? akarević, P. Radojković, J. Verdú, A. Pajuelo, F. J. Cazorla, M. Nemirovsky, and M. Valero, "Characterizing the resource-sharing levels in the ultrasparc t2 processor," in International Symposium on Microarchitecture (MICRO), 2009, pp. 481-492.
12. C. Acosta, F. J. Cazorla, A. Ramirez, and M. Valero, "Thread to core assignment in smt on-chip multiprocessors," in International Symposium on Computer Architecture and High Performance Computing (SBACPAD), 2009, pp. 67-74.
13. L. Weng and C. Liu, "On better performance from scheduling threads according to resource demands in mmmp," in International Conference on Parallel Processing Workshops (ICPPW), 2010, pp. 339-345.
14. F. J. Cazorla, A. Ramirez, M. Valero, and E. Fernandez, "Dynamically controlled resource allocation in smt processors," in International Symposium on Microarchitecture (MICRO), 2004, pp. 171-182.
15. S. Choi and D. Yeung, "Learning-based smt processor resource distribution via hill-climbing," in International Symposium on Computer Architecture (ISCA), 2006, pp. 239-251.
16. H. Wang, I. Koren, and C. M. Krishna, "An adaptive resource partitioning algorithm for smt processors," in International Conference on Parallel Architectures and Compilation Techniques (PACT), 2008, pp. 230-239.
17. M. Moreto, F. J. Cazorla, A. Ramirez, and M. Valero, in Transactions on High-Performance Embedded Architectures and Compilers III, 2011, ch. Dynamic cache partitioning based on the MLP of cache misses, pp. 3-23.
18. M. Moreto, F. J. Cazorla, R. Sakellariou, and M. Valero, "Load balancing using dynamic cache allocation," in International Conference on Computing Frontiers (CF), 2010, pp. 153-164.
19. S. Srikantaiah, M. Kandemir, and Q. Wang, "Sharp control: controlled shared cache management in chip multiprocessors," in International Symposium on Microarchitecture (MICRO), 2009, pp. 517-528.
20. R. Manikantan, K. Rajan, and R. Govindarajan, "Probabilistic shared cache management (prism)," in International Symposium on Computer Architecture (ISCA), 2012, pp. 428-439.
21. J. Chen and L. K. John, "Predictive coordination of multiple on-chip resources for chip multiprocessors," in International Conference on Supercomputing (ICS), 2011, pp. 192-201.
22. R. Bitirgen, E. Ipek, and J. F. Martinez, "Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach," in International Symposium on Microarchitecture (MICRO), 2008, pp. 318-329.
23. S. Eranian, "What can performance counters do for memory subsystem analysis?" in Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2008, pp. 26-30.
24. A. Snavely and D. M. Tullsen, "Symbiotic jobscheduling for a simultaneous mutlithreading processor," SIGPLAN Not., vol. 35, no. 11, Nov. 2000.
25. K. Luo, J. Gummaraju, and M. Franklin, "Balancing Thoughput and Fairness in SMT Processors," in International Symposium on Performance Analysis of Systems and Software (ISPASS), 2001, pp. 164-171.