Exploiting coarse-grain verification parallelism for power-efficient fault tolerance

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2005, Issue , 2005, Pages 315-325

  Rashid, M Wasiur ^a   Tan, Edwin J ^a   Huang, Michael C ^a   Albonesi, David H ^b  

^a University of Rochester   (United States)

^b Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COARSE-GRAIN VERIFICATION; HARDWARE SUPPORT; MICROARCHITECTURES; REDUNDANT EXECUTION;

COMPUTER HARDWARE; COSTS; ERROR ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 33746693677     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2005.20     Document Type: Conference Paper

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