ParTejas: A parallel simulator for multicore processors

ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2014, Pages 130-131

  Malhotra, Geetika ^a   Aggarwal, Pooja ^a   Sagar, Abhishek ^b   Sarangi, Smruti R ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^b ADOBE Systems India Private Limited   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENCY CONTROL; SYNCHRONIZATION;

CONCURRENT DATA STRUCTURES; FLEXIBLE BARRIER; HIGH-LEVEL MODELS; MULTI-CORE PROCESSOR; MULTIPLE THREADS; PARALLEL SIMULATOR; SHARED RESOURCES; SIMULATION SPEED;

JAVA PROGRAMMING LANGUAGE;

EID: 84904472479     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2014.6844470     Document Type: Conference Paper

References (6)

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