Speculative instruction validation for performance-reliability trade-off

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2008, Pages 405-414

  Kumar, Sumeet ^a   Aggarwal, Aneesh ^a  

^a State University of New York   (United States)

Author keywords

Concurrent error detection; Instruction validation; Performance reliability trade off; Reducing instruction redundancy; Redundant multi threading

Indexed keywords

COMMERCE; COMPUTER ARCHITECTURE; COMPUTERS; CONVOLUTIONAL CODES; ERROR DETECTION; ERRORS; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; REDUNDANCY;

CONCURRENT ERROR DETECTION; INSTRUCTION VALIDATION; PERFORMANCE-RELIABILITY TRADE-OFF; REDUCING INSTRUCTION REDUNDANCY; REDUNDANT MULTI-THREADING;

RELIABILITY;

EID: 57749177456     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658656     Document Type: Conference Paper

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