A 280 mV-to-1.1 v 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm tri-gate CMOS

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 1, 2013, Pages 118-127

  Hsu, Steven K ^a   Agarwal, Amit ^a   Anders, Mark A ^a   Mathew, Sanu K ^a   Kaul, Himanshu ^a   Sheikh, Farhana ^a   Krishnamurthy, Ram K ^a  

^a INTEL RESEARCH   (United States)

Author keywords

VMIN; crossbar; flip flop; level shifter; near threshold voltage (NTV); permutation; register file; Single instruction multiple data (SIMD); ultra low voltage; vector processing

Indexed keywords

LEVEL SHIFTER; NEAR-THRESHOLD VOLTAGE (NTV); PERMUTATION; REGISTER FILES; SINGLE INSTRUCTION MULTIPLE DATA; ULTRALOW VOLTAGE; VECTOR PROCESSING;

DELAY CIRCUITS; ENERGY EFFICIENCY; FLIP FLOP CIRCUITS; TREES (MATHEMATICS);

THRESHOLD VOLTAGE;

EID: 84872106745     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2222811     Document Type: Article

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