Design of embedded memory and logic based on pattern constructs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 104-105

  Morris, Daniel ^a   Vaidyanathan, Kaushik ^a   Lafferty, Neal ^b   Lai, Kafai ^b   Liebmann, Lars ^b   Pileggi, Larry ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN RULES; EMBEDDED MEMORIES; LAYOUT DESIGNS; MEMORY CIRCUITS; PROCESS CAPABILITIES;

EXPERIMENTS; MANUFACTURE;

DESIGN;

EID: 80052691209     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. L. Liebmann, L. Pileggi, J. Hibbeler, V. Rovner, T. Jhaveri, G. Northrop, "Simply to survive: Prescriptive layouts ensure profitable scaling to 32nm and beyond," SPIE Design Manufacturing Through Design-Process Integration, vol 7275, 2009.
2. T. Jhaveri et al., "Maximization of Layout Printability / Manufacturability by Extreme Regular Layout," J. Micro/Nanolithography, MEMS MOEMS 6(3), 2007.
3. A. Rosenbluth et al., "Optimum Mask and Source Patterns to Print a Given Shape," SPIE Conference on Optical Microlithography XIV, Santa Clara, USA, 27 Feb - 2 Mar 2001, v. 4346, p. 486-502.
4. W. Hinsberg, J. Cheng, H. Kim and D. Sanders, "Self- Assembling Materials for Lithographic Patterning: Overview, Status, and Moving Forward, Proc. SPIE vol. 7637, 2010.