A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Volumn , Issue , 2008, Pages 63-66

  Murachi, Yuichiro ^a   Kamino, Tetsuya ^a   Miyakoshi, Junichi ^a   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a  

^a KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; DIGITAL TELEVISION; HIGH DEFINITION TELEVISION; INDUSTRIAL ENGINEERING; MOTION ESTIMATION; RAILROAD TUNNELS; TELEVISION BROADCASTING; VIDEO SIGNAL PROCESSING; WINDOWS;

INTERNATIONAL SYMPOSIUM; VIDEO PROCESSING; VLSI DESIGNS;

STATIC RANDOM ACCESS STORAGE;

EID: 50649113516     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2008.4542413     Document Type: Conference Paper

References (3)

1. ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, 2003.
2. J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M.Yoshimoto, "A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing," IEICE Trans. Electron., vol.E89-C,no.11, pp.1629-1636, November 2006.
3. Y. Murachi, K. Mizuno, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, T. Kamino, H. Kawaguchi, and M. Yoshimoto "A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding", 2008 IEEE International Symposium on Circuits and Systems, May 2008 (to be held).