64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1682-1688

  Heald, Raymond ^a,d   Shin, Ken ^a,b,e   Reddy, Vinita ^a,f,g,h   Kao, I Feng ^a,i,j   Khan, Masood ^b,c   Lynch, William L ^a   Lauterbach, Gary ^a   Petolino, Joe ^a  

^a SUN MICROSYSTEMS   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c Hitachi Micro Systems Inc   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^f UNIVERSITY OF DELHI   (India)

^g UNIVERSITY OF WISCONSIN MADISON   (United States)

^h NXP SEMICONDUCTORS   (Netherlands)

ⁱ UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^j STANFORD UNIVERSITY   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BUFFER STORAGE; DECODING; PIPELINE PROCESSING SYSTEMS;

SUM-ADDRESSED-MEMORY CACHE;

RANDOM ACCESS STORAGE;

EID: 0032204698     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726558     Document Type: Article

References (8)

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