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Volumn 57, Issue , 2014, Pages 232-233

A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS;

EID: 84898064925     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757413     Document Type: Conference Paper
Times cited : (81)

References (11)
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  • 2
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    • Feb.
    • F. Hamzaoglu et al., "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-k Metal-Gate CMOS Technology", ISSCC Dig. Tech. Papers, pp. 376-621, Feb. 2008.
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    • Hamzaoglu, F.1
  • 3
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    • Feb.
    • H. Pilo et al., "A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management", ISSCC Dig. Tech. Papers, pp. 378-621, Feb. 2008.
    • (2008) ISSCC Dig. Tech. Papers , pp. 378-621
    • Pilo, H.1
  • 4
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    • Feb.
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  • 5
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    • Feb.
    • Y. Wang et al., "A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management", ISSCC Dig. Tech. Papers, pp. 456-457, Feb. 2009.
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    • Wang, Y.1
  • 6
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    • Feb.
    • 2 cell in 32nm high-k metal-gate CMOS", ISSCC Dig. Tech. Papers, pp. 348-349, Feb. 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 348-349
    • Fujimura, Y.1
  • 7
    • 79955723758 scopus 로고    scopus 로고
    • A 64Mb SRAM in 32nm high-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements
    • Feb.
    • H. Pilo et al., "A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements", ISSCC Dig. Tech. Papers, pp. 254-256, Feb. 2011.
    • (2011) ISSCC Dig. Tech. Papers , pp. 254-256
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  • 8
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    • Feb.
    • E. Karl et al., "A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry", ISSCC Dig. Tech. Papers, pp. 230-232, Feb. 2012.
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  • 9
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    • Feb.
    • H. Pilo et al., "A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction", ISSCC Dig. Tech. Papers, pp. 322-323, Feb. 2013.
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  • 11
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.