Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7974, Issue , 2011, Pages

  Rovner, Vyacheslav V ^a,b   Jhaveri, Tejas ^a,b   Morris, Daniel ^b   Strojwas, Andrzej ^a,b   Pileggi, Larry ^b  

^a PDF SOLUTIONS INC   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Circuit layout co optimization; DFM; Layout pattern; Pattern fill; Regular design fabric; SMO

Indexed keywords

CO-OPTIMIZATION; DFM; LAYOUT PATTERN; PATTERN FILL; REGULAR DESIGN FABRIC; SMO;

DIGITAL INTEGRATED CIRCUITS; MACHINE DESIGN; MASKS; OPTIMIZATION;

CHEMICAL MECHANICAL POLISHING;

EID: 79955804473     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.879514     Document Type: Conference Paper

References (10)

1. W. Maly, H. Heineken, J. Khare, and P. K. Nag, "Design for manufacturability in submicron domain," in Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD'96), 1996, pp. 690-697.
2. L. W. Liebmann, "Layout impact of resolution enhancement techniques: Impediment or opportunity?," in Proc. International Symposium on Physical Design (ISPD'03), 2003, pp. 110-117.
3. M. Lavin, F. L. Heng, and G. Northrop, "Backend CAD for "restrictive design rules"," in Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD'04), 2004, pp. 739-746. (Pubitemid 40449314)
4. A. J. Strojwas, T. Jhaveri, V. Rovner, and L. Pileggi, "Creating an affordable 22nm node using design-lithography co-optimization," in Proc. 46th ACM/IEEE Design Automation Conference (DAC'09), 2009, pp. 95-96.
5. L. Liebmann et al., "Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond," in Proc. SPIE Design for Manufacturability through Design-Process Integration III, vol. 7275, 2009.
6. T. Jhaveri et al., "Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings," IEEE Transactions Computer Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, pp. 509-527, April 2010.
7. Tejas Jhaveri, "Regular Design Fabrics for Low Cost Scaling of Integrated Circuits," Carnegie Mellon University, PhD Thesis 2009.
8. Michal Palusinki, "Applications of Regularity in IC Design and Verification," Carnegie Mellon University, Phd Thesis 2007.
9. Dick James, "Intel pushes lithography limits, co-optimizes design/layout/process at 45nm," Solid State Technology, vol. 51, no. 3, March 2008.
10. T. Jhaveri and A. Strojwas, "Using Templates and Connectors for Layout Pattern Minimization in 20nm and Below Technology Nodes," in Proc. SPIE Design for Manufacturability through Design-Process Integration V, 2011.