Device and circuit-level analog performance trade-offs: A comparative study of planar bulk FETs versus FinFETs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 898-901

  Subramanian, V ^a,b   Parvais, B ^a   Borremans, J ^a,c   Mercha, A ^a   Linten, D ^a,c   Wambacq, P ^a,c   Loo, J ^a   Dehan, M ^a   Collaert, N ^a   Kubicek, S ^a   Lander, R J P ^d   Hooker, J C ^d   Cubaynes, F N ^d   Donnay, S ^a   Jurczak, M ^a   Groeseneken, G ^a,b   Sansen, W ^b   Decoutere, S ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; DIGITAL CIRCUITS; GAIN CONTROL; LEAKAGE CURRENTS; TRANSCONDUCTANCE;

ANALOG PERFORMANCE; FINFET DEVICES; POWER TRADE-OFF; VOLTAGE GAIN;

FIELD EFFECT TRANSISTORS;

EID: 33846573973     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. V.Kilchytska, N.Collaert, R.Rooyackers, D.Lederer, J-P.Raskin and D.Flandre, "Perspectives of FinFETs for analog applications", IEEE Trans. Electr. Dev vol 48, pp. 65-68 (2004)
2. A.Dixit, K.G.Anil, A.Mercha, N.Collaert, S.Brus, O.Richard et al, "Towards optimally shaped fins in p-channel tri-gate FETs: Can fin height be reduced further?", Proc. of Tech. Papers, Intl. Symposium on VLSI Tech., pp. 112-113 (2005)
3. K.Henson, R.J.P.Lander, M.Demand, C.J.J.Dachs, B.Kaczer et al, "45nm nMOSFET with Metal Gate on thin SiON driving 1150μA/μm and off-state of 10 nA/μm", IEDM Tech. Dig., pp. 851-854, (2004)
4. ITRS roadmap, 2004 edition (http://public.itrs.net)
5. A.Dixit, A.Kottantharayil, N.Collaert, M.Goodwin, M.Jurczak and K.De Meyer, "Analysis of the parasitic S/D resistance in MuGFETs", Trans. Electr. Dev., vol. 52. pp.832-840 (2005)