Design technology co-optimization in technology definition for 22nm and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 112-113

  Northrop, Greg ^a  

^a IBM   (United States)

Author keywords

CMOS; design rule; lithography; RDR; scaling

Indexed keywords

CMOS; CMOS TECHNOLOGY; CO-OPTIMIZATION; CRITICAL LEVEL; DESIGN AND TECHNOLOGY; DESIGN RULE; DESIGN RULES; DESIGN TECHNOLOGIES; OPTIMAL SOLUTIONS; PHYSICAL DIMENSIONS; PRAGMATIC PROCESS; RDR; SCALING;

CMOS INTEGRATED CIRCUITS; DESIGN; OPTIMIZATION; VLSI CIRCUITS;

TECHNOLOGY;

EID: 80052676645     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri and Greg Northrop, "Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond", Proc. SPIE 7275, 72750A (2009); doi:10.1117/12.814701
2. T. Jhaveri, V. Rovner, L. Liebmann, L. Pileggi, A.J. Strojwas, J.D. Hibbeler, Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 29 Issue: 4, April 2010.