A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 21-24

  Wissel, Larry ^a   Pilo, Harold ^a   Leblanc, Chris ^a   Wang, Xiaopeng ^a   Lamphier, Steve ^a   Fragano, Michael ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

65NM CMOS TECHNOLOGY; ACCESS TIME; COLUMN DIMENSIONS; DESIGN TECHNIQUE; SCALABLE ARCHITECTURES; SRAM MACRO;

CMOS INTEGRATED CIRCUITS;

EID: 77954918256     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405673     Document Type: Conference Paper

References (6)

1. H. Pilo et al., "A 0. 9ns Random Cycle 36Mb Network SRAM with 33mW Standby Power, " IEEE VLSI Circuits Symposium, pp. 284-287, June 2004
2. F. Duan et. al., "Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability, " Proceedings of the 4th International Symposium on Quality Electronic Design, pp. 119-124, March 2003
3. G. Braceras et al., "A 940MHz Data-Rate 8Mb CMOS SRAM, " IEEE International Solid-State Circuits Conference, pp. 198-199, Feb. 1999
4. H. Pilo et al., "A 300MHz, 3. 3V 1Mb SRAM Fabricated in a 0. 5m Process, " IEEE International Solid-State Circuits Conference, pp. 148-149, Feb. 1996
5. J. Davis et al., "A 5. 6GHz 64kB Dual-Read Data Cache for the POWER6 Processor, " IEEE International Solid-State Circuits Conference, pp. 622-623, Feb. 2006
6. J. Barth et al., "A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write, " IEEE International