Differentiated communication services for NoC-Based MPSoCs

IEEE Transactions on Computers

Volumn 63, Issue 3, 2014, Pages 595-608

  Carara, Everton Alceu ^a   Calazans, Ney Laert Vilar ^b   Moraes, Fernando Gehm ^b  

^a FEDERAL UNIVERSITY OF SANTA MARIA   (Brazil)

^b PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

API; composability; MPSoC; NoC; QoS

Indexed keywords

APPLICATION PROGRAMMING INTERFACES (API); MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY OF SERVICE;

ADAPTIVE ROUTING ALGORITHM; API; APPLICATION DEVELOPERS; COMMUNICATION INFRASTRUCTURE; COMPOSABILITY; MPSOC; NOC; SYNTHETIC APPLICATION;

COMMUNICATION;

EID: 84897521925     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.123     Document Type: Article

References (57)

1. W. Wolf, A. Jerraya, and G. Martin, "Multiprocessor System-on- Chip (MPSoC) Technology," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 10, pp. 1701-1713, Oct. 2008.
2. L. Benini and G. Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
3. W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Design Automation Conf. (DAC), pp. 684-689, 2001.
4. P. Guerrier and A. Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 250-256, 2000.
5. S. Pasricha and N. Dutt, On-Chip Communication Architectures- System on Chip Interconnect. Morgan Kaufmann Publishers, 2008.
6. Int'l Technology Roadmap for Semiconductors, "2009 Update- System Drivers," http://www.itrs.net/Links/2010ITRS/ Home2010.htm, 2012.
7. M. Coppola, M. Grammatikakis, R. Locatelli, G. Maruccia, and L. Pieralisi, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC. CRC Press, 2008.
8. Tilera Corporation, "TILE64 Processor," product brief description, 2007.
9. D. Wentzlaff, P. Griffin, H. Hoffmann, B. Liewei, B. Edwards, C. Ramey, M. Mattina, M. Chyi-Chang, J.F. Brown, and A. Agarwal, "On-Chip Interconnection Architecture of the Tile Processor," IEEE Micro, vol. 27, no. 5, pp. 15-31, Sept./Oct. 2007.
10. A. Kumar, A. Hansson, J. Huisken, and H. Corporaal, "An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 117-122, 2007.
11. "SiliconHive," http://www.silicon-hive.com, 2011.
12. K. Goossens, J. Dielissen, and A. Radulescu, "Aethereal Network- on-Chip: Concepts, Architectures, and Implementations," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, Sept./Oct. 2005.
13. J. Murilo, "HW-SW Components for Parallel Embedded Computing on NoC-Based MPSoCS," PhD thesis, Universitat Autonoma de Barcelona, p. 218, 2009.
14. D. Bertozzi and L. Benini, "Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip," Circuits and Systems Magazine, vol. 4, no. 2, pp. 18-31, 2004.
15. A.K. Singh, A. Kumar, T. Srikanthan, and Y. Ha, "Mapping Real- Life Applications on Run-Time Reconfigurable NoC-Based MPSoC on FPGA," Proc. Int'l Conf. Field-Programmable Technology (FPT), pp. 365-368, 2010.
16. Z.J. Yang, A. Kumar, and Y. Ha, "An Area-Efficient Dynamically Reconfigurable Spatial Division Multiplexing Network-on-Chip with Static Throughput Guarantee," Proc. Int'l Conf. Field- Programmable Technology (FPT), pp 389-392, 2010.
17. G.M. Almeida, G. Sassatelli, P. Benoit, N. Saint-Jean, S. Varyani, L. Torres, and M. Robert, "An Adaptive Message Passing MPSoC Framework," Int'l J. Reconfigurable Computing, vol. 1, p. 20, 2009.
18. F. Moraes, N. Calazans, A. Mello, L. Moller, and L. Ost, "HERMES: An Infrastructure for Low Area Overhead Packet- Switching Networks on Chip," Integration the VLSI J., vol. 38, no. 1, pp. 69-93, 2004.
19. S. Yang, S.B. Furber, and L.A. Plana, "Adaptive Admission Control on the SpiNNaker MPSoC," Proc. IEEE Int'l System-on- Chip Conf. (SOCC), pp. 243-246, 2009.
20. B. Ahmad, A.T. Erdogan, and S. Khawam, "Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC," Proc. First NASA/ESA Conf. Adaptive Hardware and Systems (AHS), pp. 405-411, 2006.
21. R. Obermaisser, H. Kopetz, and C. Paukovits, "A Cross-Domain Multiprocessor System-on-a-Chip for Embedded Real-Time Systems," IEEE Trans. Industrial Informatics, vol. 6, no. 4, pp. 548-567, Nov. 2010.
22. E. Onieva, D.A. Pelta, J. Alonso, V. Milanes, and J. Pere, "A Modular Parametric Architecture for the TORCS Racing Engine," Proc. Fifth Int'l Conf. Computational Intelligence and Games (CIG), pp. 256-262, 2009.
23. A. Motakis, G. Kornaros, and M. Coppola, "Dynamic Resource Management in Modern Multicore SoCs by Exposing NoC Services," Proc. Sixth Int'l Workshop Reconfigurable Comm.-Centric Systems-on-Chip (ReCoSoC), p. 6, 2011.
24. E. Silva, D. Barcelos, F. Wagner, and C. Pereira, "A Virtual Platform for Multiprocessor Real-Time Embedded Systems," Proc. Sixth Int'l Workshop Java Technologies for Real-Time and Embedded Systems (JTRES), p. 6, 2008.
25. C.A. Zeferino and A.A. Susin, "SoCIN: A Parametric and Scalable Network-on-Chip," Proc. Sixth Int'l Workshop Java Technologies for Real-Time and Embedded Systems (SBCCI), pp. 169-174, 2003.
26. G. Bolleta, B. Brosgol, S. Furr, D. Hardin, P. Dibble, J. Gosling, and M. Turnbull, "The Real-Time Specification for Java," www.rtsj.org, 2010.
27. J. Joven, O. Font-Bach, D. Castells-Rufas, R. Martinez, L. Teres, and J. Carrabina, "xENOC-An eXperimental Network-on-Chip Environment for Parallel Distributed Computing on NoC-Based MPSoC Architectures," Proc. 16th Euromicro Conf. Parallel, Distributed and Network-Based Processing (PDP), pp. 141-148, 2008.
28. K. Kumar, B. Mesman, B. Theelen, H. Corporaal, and H. Ha, "Analyzing Composability of Applications on MPSoC Platforms," J. Systems Architecture, vol. 54, nos. 3/4, pp. 369-383, 2008.
29. A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, and P. Wielage, "An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 878-883, 2004.
30. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers, 2003.
31. E. Salminen, A. Kulmala, and T. Hamalainen, "Survey of Network-on-Chip Proposals," white paper, OCP-IP, 2008.
32. A. Agarwal, C. Iskander, and R. Shankar, "Survey of Network on Chip (NoC) Architectures & Contributions," J. Eng., Computing and Architecture, vol. 2, no. 1, 2009.
33. E. Carara, N. Calazans, and F. Moraes, "A New Router Architecture for High-Performance Intrachip Networks," J. Integrated Circuits and Systems, vol. 3, no. 1, pp. 23-31, 2008.
34. E. Nilsson, M. Millberg, J. Oberg, and A. Jantsch, "Load Distribution with the Proximity Congestion Awareness in a Network on Chip," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 1126-1127, 2003.
35. J. Hu and R. Marculescu, "DyAD-Smart Routing for Networkson- Chip," Proc. 41st Design Automation Conf. (DAC), pp. 260-263, 2004.
36. T. Ye, L. Benini, and G. Micheli, "Packetization and Routing Analysis of On-Chip Multiprocessor Networks," J. Systems Architecture, vol. 50, nos. 2/3, pp. 81-104, 2004.
37. M. Li, Q. Zeng, and W. Jone, "DyXY-A Proximity Congestion- Aware Deadlock-Free Dynamic Routing Method for Networks on Chip," Proc. ACM/IEEE 43rd Design Automation Conf. (DAC), pp. 849-852, 2006.
38. A. Sobhani, M. Daneshtalab, M. Neishaburi, M. Mottaghi, A. Afzali-Kusha, O. Fatemi, and Z. Navabi, "Dynamic Routing Algorithm for Avoiding Hot Spots in On-Chip Networks," Proc. Int'l Conf. Design and Test of Integrated Systems Nanoscale Technology (DTIS), pp. 179-183, 2006.
39. E. Carara and F. Moraes, "Flow Oriented Routing for NOCS," Proc. IEEE Int'l System-on-Chip Conf. (SOCC), pp. 367-370, 2010.
40. G. Ascia, V. Catania, M. Palesi, and D. Patti, "Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip," IEEE Trans. Computers, vol. 57, no. 6, pp. 809- 820, June 2008.
41. G. Chiu, "The Odd-Even Turn Model for Adaptive Routing," IEEE Trans. Parallel and Distributed Systems, vol. 7, no. 11, pp. 729-738, July 2000.
42. C.J. Glass and L.M. Ni, "The Turn Model for Adaptive Routing," J. ACM, vol. 41, no. 5, pp. 874-902, 1994.
43. X. Lin, P.K. McKinley, and L.M. Ni, "Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers," IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 8, pp. 793-804, Aug. 1994.
44. F. Gilabert, M.E. Gomez, S. Medardoni, and D. Bertozzi, "Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-Processor Systems-on-Chip," Proc. ACM/IEEE Fourt Symp. Networks-on-Chip (NOCS), pp. 165- 172, 2010.
45. Y.J. Yoon, N. Concer, M. Petracca, and L. Carloni, "Virtual Channels vs. Multiple Physical Networks: A Comparative Analysis," Proc. 47th Design Automation Conf. (DAC), pp. 162-165, 2010.
46. M.R. Kakoee, V. Bertacco, and L. Benini, "ReliNoC: A Reliable Network for Priority-Based On-Chip Communication," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 491-496, 2011.
47. E. Carara, G. Almeida, G. Sassatelli, and F. Moraes, "Achieving Composability in NoC-Based MPSoCs through QoS Management at Software Level," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 407-412, 2011.
48. A. Mello, L. Tedesco, N. Calazans, and F. Moraes, "Evaluation of Current QoS Mechanisms in Networks on Chip," Proc. Int'l Symp. Systems-on-Chip (SOC), 2006.
49. D. Wiklund and D. Liu, "SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems," Proc. Int'l Parallel and Distributed Processing Symp. (IPDPS), 2003.
50. E. Fernandez-Alonso, D. Castells-Rufas, S. Risueno, J. Carrabina, and J. Joven, "A NoC-Based Multi-{Soft}core with 16 Cores," Proc. 17th IEEE Int'l Conf. Electronics, Circuits, and Systems (ICECS), pp. 259-252, 2010.
51. F. Fu, S. Sun, X. Hu, J. Song, J. Wang, and M. Yu, "MMPI: A Flexible and Efficient Multiprocessor Message Passing Interface for NoC-Based MPSoC," Proc. IEEE Int'l System-on-Chip Conf. (SOCC), pp. 359-362, 2010.
52. E. Carara and F. Moraes, "Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip," Proc. IEEE CS Ann. Symp. Very Large Scale Integration (ISVLSI), pp. 341-346, 2008.
53. M. Daneshtalab, M. Ebrahimi, T.C. Xu, P. Liljeberg, and H. Tenhunen, "A Generic Adaptive Path-Based Routing Method for Mpsocs," J. Systems Architecture, vol. 57, no. 1, pp. 109-120, 2011.
54. S. Rhoads, "Plasma-Most MIPS- I Opcodes," http://www. opencores.org/project,plasma, 2012.
55. Texas Instruments, "Wireless Terminals Solutions Guide," http:// focus.ti.com/pdfs/vf/wireless/ti-wireless-solutions-guide.pdf, 2012.
56. E. Carara, R. Oliveira, N. Calazans, and F. Moraes, "HeMPS-A Framework for NoC-Based MPSoC Generation," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), pp. 1345-1348, 2009.
57. T.M. Chaves, E.A Carara, and F.G. Moraes, "Energy-Efficient Cache Coherence Protocol for NoC-Based MPSoCs," Proc. 24th Symp. Integrated Circuits and Systems Design (SBCCI), pp. 215-220, 2011.