HeMPS - A framework for NoC-based MPSoC generation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 1345-1348

  Carara, Everton A ^a   De Oliveira, Roberto P ^a   Calazans, Ney L V ^a   Moraes, Fernando G ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACT MODELS; APPLICATION MAPPING; BUS-BASED; CAD TOOL; COMMUNICATION ARCHITECTURES; DESIGN SPACE EXPLORATION; DESIGN SPACES; DYNAMIC MAPPING; EXECUTION TIME; GRAPHICAL TOOLS; MULTIPROCESSOR-SYSTEM; RUNNING APPLICATIONS; SIMULATION MODEL; SIMULATION TIME REDUCTION; STATIC AND DYNAMIC; SYSTEM VERIFICATIONS;

ABSTRACTING; COMPUTER AIDED DESIGN; ELECTRIC NETWORK TOPOLOGY; MAPPING; SIMULATORS; SPACE RESEARCH;

EMBEDDED SYSTEMS;

EID: 70350158179     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118013     Document Type: Conference Paper

References (8)

1. Lyonnard, D. et al "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip". In: DAC, 2001, pp. 518-523.
2. Samahi, A.; Bourennane, E. "Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform". In: AHS, 2007, pp. 379-385.
3. Joven, J.; Carrabina, J.; et al "xENOC - An eXperimental Network-on-Chip Enviroment for Parallel Distributed Computing on NoC-based MPSoC Archtectures". In: Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2008, pp. 141-148.
4. Moraes, F.; et al. "HERMES: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip". Integration the VLSI Journal, 38(1), Oct. 2004, pp. 69-93.
5. OpenCores, www.opencores.org.
6. G. Kahn. "The semantics of a simple language for parallel programming". In: Information Processing, 1974, pp 471-475.
7. Altera, www.altera.com
8. Xilinx, www.xilinx.com