An area-efficient dynamically reconfigurable spatial division multiplexing Network-on-Chip with static throughput guarantee

Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Volumn , Issue , 2010, Pages 389-392

  Yang, Zhiyao Joseph ^a   Kumar, Akash ^a,b   Ha, Yajun ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Dynamic reconfiguration; FPGA; Network on Chip; Spatial division multiplexing; Throughput guarantee

Indexed keywords

AREA EFFICIENT; AREA REDUCTION; DYNAMIC RE-CONFIGURATION; FPGA; GUARANTEED SERVICE; MULTIPROCESSOR-SYSTEM; NETWORK INTERFACE; NETWORK ON CHIP; RE-CONFIGURABLE; SERIALIZERS; SPATIAL DIVISION MULTIPLEXING;

DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SERVERS; SPACE DIVISION MULTIPLE ACCESS; THROUGHPUT; TIME DIVISION MULTIPLEXING; VLSI CIRCUITS;

ROUTERS;

EID: 79551541248     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2010.5681443     Document Type: Conference Paper

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