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Volumn , Issue , 2009, Pages 243-246

Adaptive admission control on the SpiNNaker MPSoC

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ADMISSION CONTROLS; END-TO-END COMMUNICATION; FAIR BANDWIDTH ALLOCATION; HDL MODELS; MATLAB MODELS; MULTIPROCESSOR-SYSTEM; PROCESSING NODES; PROTOTYPING; SYSTEM MODELS;

EID: 77949608102     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCCON.2009.5398050     Document Type: Conference Paper
Times cited : (2)

References (5)
  • 1
    • 56349117789 scopus 로고    scopus 로고
    • On-Chip and Inter-Chip networks for Modelling Large-Scale Neural Systems
    • ISCAS, May
    • Steve Furber, Steve Temple and Andrew Brown, "On-Chip and Inter-Chip networks for Modelling Large-Scale Neural Systems", International Symposium on Circuits and Systems, ISCAS, pages 21-24, May 2006.
    • (2006) International Symposium on Circuits and Systems , pp. 21-24
    • Furber, S.1    Temple, S.2    Brown, A.3
  • 2
    • 0036761283 scopus 로고    scopus 로고
    • Chain: A Delay-insensitive chip area interconnect
    • Sept
    • John Bainbridge and Steve Furber, "Chain: a Delay-insensitive chip area interconnect," IEEE Micro, volume 22, pages 16-23, Sept. 2004.
    • (2004) IEEE Micro , vol.22 , pp. 16-23
    • Bainbridge, J.1    Furber, S.2
  • 5
    • 77949587000 scopus 로고    scopus 로고
    • Building and Analyzing On-Chip Networks using CHAIN architect
    • Silistix Ltd, Technical report, V1.2.5, AUG
    • Silistix Ltd., "Building and Analyzing On-Chip Networks using CHAIN architect", Technical report, V1.2.5, AUG 2008
    • (2008)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.