-
1
-
-
70649092154
-
Rodinia: A benchmark suite for heterogeneous computing
-
S. Che, M. Boyer, J. Meng, D. Tarjan, J. Sheaffer, S.-H. Lee, and K. Skadron, "Rodinia: A benchmark suite for heterogeneous computing," in IEEE International Symposium on Workload Characterization (IISWC-2009), October 2009.
-
IEEE International Symposium on Workload Characterization (IISWC-2009), October 2009
-
-
Che, S.1
Boyer, M.2
Meng, J.3
Tarjan, D.4
Sheaffer, J.5
Lee, S.-H.6
Skadron, K.7
-
2
-
-
63549097654
-
A MapReduce Framework on Graphics Processors
-
B. He, W. Fang, Q. Luo, N. Govindaraju, and T. Wang, "A MapReduce Framework on Graphics Processors," in 17th International Conference on Parallel Architecture and Compilation Techniques (PACT-17), 2008.
-
17th International Conference on Parallel Architecture and Compilation Techniques (PACT-17), 2008
-
-
He, B.1
Fang, W.2
Luo, Q.3
Govindaraju, N.4
Wang, T.5
-
4
-
-
47349104432
-
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
-
W. W. Fung, I. Sham, G. Yuan, and T. M. Aamodt, "Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow," in 40th International Symposium on Microarchitecture (MICRO-40), December 2007.
-
40th International Symposium on Microarchitecture (MICRO-40), December 2007
-
-
Fung, W.W.1
Sham, I.2
Yuan, G.3
Aamodt, T.M.4
-
5
-
-
74049151553
-
Increasing memory miss tolerance for SIMD cores
-
D. Tarjan, J. Meng, and K. Skadron, "Increasing memory miss tolerance for SIMD cores," in Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC-09), 2009.
-
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC-09), 2009
-
-
Tarjan, D.1
Meng, J.2
Skadron, K.3
-
16
-
-
80054875176
-
GPUs and the Future of Parallel Computing
-
October
-
S. Keckler, W. Dally, B. Khailany, M. Garland, and D. Glasco, "GPUs and the Future of Parallel Computing," in IEEE Micro, October 2011.
-
(2011)
IEEE Micro
-
-
Keckler, S.1
Dally, W.2
Khailany, B.3
Garland, M.4
Glasco, D.5
-
18
-
-
84864862775
-
The dynamic granularity memory system
-
D. H. Yoon, M. Sullivan, M. K. Jeong, and M. Erez, "The dynamic granularity memory system," in 39th International Symposium on Computer Architecture (ISCA-39), 2012.
-
39th International Symposium on Computer Architecture (ISCA-39), 2012
-
-
Yoon, D.H.1
Sullivan, M.2
Jeong, M.K.3
Erez, M.4
-
25
-
-
74049087888
-
Future scaling of processor-memmory interfaces
-
J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber, "Future scaling of processor-memmory interfaces," in Proc. the Int'l Conf. High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009.
-
Proc. the Int'l Conf. High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009
-
-
Ahn, J.H.1
Jouppi, N.P.2
Kozyrakis, C.3
Leverich, J.4
Schreiber, R.S.5
-
26
-
-
67650604446
-
Multicore DIMM: An energy efficient memory module with independently controlled DRAMs
-
Jan.-Jun.
-
J. H. Ahn, J. Leverich, R. Schreiber, and N. P. Jouppi, "Multicore DIMM: An energy efficient memory module with independently controlled DRAMs," IEEE Computer Architecture Letters, vol. 8, no. 1, pp. 5-8, Jan.-Jun. 2009.
-
(2009)
IEEE Computer Architecture Letters
, vol.8
, Issue.1
, pp. 5-8
-
-
Ahn, J.H.1
Leverich, J.2
Schreiber, R.3
Jouppi, N.P.4
-
30
-
-
77951180817
-
Instruction set innovations for the Convey HC-1 computer
-
T. M. Brewer, "Instruction set innovations for the Convey HC-1 computer," IEEE Micro, vol. 30, no. 2, pp. 70-79, 2010.
-
(2010)
IEEE Micro
, vol.30
, Issue.2
, pp. 70-79
-
-
Brewer, T.M.1
-
31
-
-
0002388384
-
Structural aspects of the system/360 model 85, part II: The cache
-
J. S. Liptay, "Structural aspects of the system/360 model 85, part II: The cache," IBM Systems Journal, vol. 7, pp. 15-21, 1968.
-
(1968)
IBM Systems Journal
, vol.7
, pp. 15-21
-
-
Liptay, J.S.1
-
32
-
-
84877700379
-
Mage: Adaptive granularity and ecc for resilient and power efficient memory systems
-
IEEE
-
S. Li and et al., "Mage: adaptive granularity and ecc for resilient and power efficient memory systems," in High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for. IEEE, 2012, pp. 1-11.
-
(2012)
High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for
, pp. 1-11
-
-
Li, S.1
-
33
-
-
84892558405
-
The Cray Black Widow: A highly scalable vector multiprocessor
-
D. Abts and et al., "The Cray Black Widow: A highly scalable vector multiprocessor," in Proc. the Int'l Conf. High Performance Computing, Networking, Storage, and Analysis (SC), Nov. 2007.
-
Proc. the Int'l Conf. High Performance Computing, Networking, Storage, and Analysis (SC), Nov. 2007
-
-
Abts, D.1
-
35
-
-
2342482320
-
Accurate and complexity-effective spatial pattern prediction
-
C. Chen, S.-H. Yang, B. Falsafi, and A. Moshovos, "Accurate and complexity-effective spatial pattern prediction," in 10th International Symposium on High Performance Computer Architecture (HPCA-10), 2004.
-
10th International Symposium on High Performance Computer Architecture (HPCA-10), 2004
-
-
Chen, C.1
Yang, S.-H.2
Falsafi, B.3
Moshovos, A.4
-
37
-
-
0014814325
-
Space/Time Trade-Offs in Hash Coding with Allowable Errors
-
B. Bloom, "Space/Time Trade-Offs in Hash Coding with Allowable Errors," in ACM Communications, 1970.
-
(1970)
ACM Communications
-
-
Bloom, B.1
-
38
-
-
0034206002
-
Summary cache: A scalable wide-area web cache sharing protocol
-
L. Fan, P. Cao, J. Almeida, and A. Z. Broder, "Summary cache: a scalable wide-area web cache sharing protocol," IEEE/ACM Transactions on Networking (TON), vol. 8, no. 3, pp. 281-293, 2000.
-
(2000)
IEEE/ACM Transactions on Networking (TON)
, vol.8
, Issue.3
, pp. 281-293
-
-
Fan, L.1
Cao, P.2
Almeida, J.3
Broder, A.Z.4
-
39
-
-
0031366315
-
Efficient Hardware Hashing Functions for High Performance Computers
-
M. Ramakrishna and et al., "Efficient Hardware Hashing Functions for High Performance Computers," in IEEE Transactions on Computers, 1997.
-
(1997)
IEEE Transactions on Computers
-
-
Ramakrishna, M.1
-
40
-
-
0030672489
-
The agree predictor: A mechanism for reducing negative branch history interference
-
E. Sprangle, R. S. Chappell, M. Alsup, and Y. N. Patt, "The agree predictor: A mechanism for reducing negative branch history interference," in 17th International Symposium on Computer Architecture (ISCA-17), 1997.
-
17th International Symposium on Computer Architecture (ISCA-17), 1997
-
-
Sprangle, E.1
Chappell, R.S.2
Alsup, M.3
Patt, Y.N.4
-
41
-
-
70349169075
-
Analyzing CUDA workloads using a detailed GPU simulator
-
A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt, "Analyzing CUDA workloads using a detailed GPU simulator," in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2009), April 2009.
-
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2009), April 2009
-
-
Bakhoda, A.1
Yuan, G.2
Fung, W.3
Wong, H.4
Aamodt, T.5
-
42
-
-
84892547793
-
-
"GPGPU-Sim," http://www.gpgpu-sim.org.
-
GPGPU-Sim
-
-
-
43
-
-
84892560748
-
-
"DrSim," http://lph.ece.utexas.edu/public/DrSim.
-
DrSim
-
-
-
44
-
-
84860328391
-
Balancing DRAM Locality and Parallelism in Shared Memory CMP Systems
-
M. K. Jeong, D. H. Yoon, D. Sunwoo, M. Sullivan, I. Lee, and M. Erez, "Balancing DRAM Locality and Parallelism in Shared Memory CMP Systems," in 18th International Symposium on High Performance Computer Architecture (HPCA-18), February 2012.
-
18th International Symposium on High Performance Computer Architecture (HPCA-18), February 2012
-
-
Jeong, M.K.1
Yoon, D.H.2
Sunwoo, D.3
Sullivan, M.4
Lee, I.5
Erez, M.6
-
45
-
-
78650867466
-
A 7Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
-
T.-Y. Oh and et al., "A 7Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction," in IEEE Journal of Solid-State Circuits, 2011.
-
(2011)
IEEE Journal of Solid-State Circuits
-
-
Oh, T.-Y.1
-
46
-
-
84881141803
-
-
"GPGPU-Sim Manual," http://www.gpgpu-sim.org/manual.
-
GPGPU-Sim Manual
-
-
-
49
-
-
38849131252
-
High-throughput sequence alignment using graphics processing units
-
M. Schatz, C. Trapnell, A. Delcher, and A. Varshney, "High- throughput sequence alignment using graphics processing units," BMC Bioinformatics, vol. 8, no. 1, p. 474, 2007.
-
(2007)
BMC Bioinformatics
, vol.8
, Issue.1
, pp. 474
-
-
Schatz, M.1
Trapnell, C.2
Delcher, A.3
Varshney, A.4
-
50
-
-
80052533471
-
Energy-efficient mechanisms for managing thread context in throughput processors
-
M. Gebhart, D. Johnson, D. Tarjan, S. Keckler, W. Dally, E. Lindholm, and K. Skadron, "Energy-efficient mechanisms for managing thread context in throughput processors," in 38th International Symposium on Computer Architecture (ISCA-38), 2011.
-
38th International Symposium on Computer Architecture (ISCA-38), 2011
-
-
Gebhart, M.1
Johnson, D.2
Tarjan, D.3
Keckler, S.4
Dally, W.5
Lindholm, E.6
Skadron, K.7
-
60
-
-
8344271981
-
Approximate caches for packet classification
-
IEEE
-
F. Chang, W.-c. Feng, and K. Li, "Approximate caches for packet classification," in INFOCOM 2004. Twenty-third AnnualJoint Conference of the IEEE Computer and Communications Societies, vol. 4. IEEE, 2004, pp. 2196-2207.
-
(2004)
INFOCOM 2004. Twenty-third AnnualJoint Conference of the IEEE Computer and Communications Societies
, vol.4
, pp. 2196-2207
-
-
Chang, F.1
Feng, W.-C.2
Li, K.3
-
62
-
-
72949105570
-
Aging bloom filter with two active buffers for dynamic sets
-
M. Yoon, "Aging bloom filter with two active buffers for dynamic sets," Knowledge and Data Engineering, IEEE Transactions on, vol. 22, no. 1, pp. 134-138, 2010.
-
(2010)
Knowledge and Data Engineering, IEEE Transactions on
, vol.22
, Issue.1
, pp. 134-138
-
-
Yoon, M.1
|