Thread block compaction for efficient SIMT control flow

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 25-36

  Fung, Wilson W L ^a   Aamodt, Tor M ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPACTION MECHANISMS; CONTROL FLOWS; GRAPHICS PROCESSOR UNITS; HARDWARE COST; LARGE GROUPS; MANY-CORE; MULTIPLE DATA; PER UNIT; PROCESSING UNITS; PROGRAMMING MODELS; RECONVERGENCE; SCRATCH PAD MEMORY; SIMULATION RESULT;

COMPACTION; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING; PROGRAM PROCESSORS;

WEAVING;

EID: 79955923056     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749714     Document Type: Conference Paper

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