Improving GPU performance via large warps and two-level warp scheduling

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 308-317

  Narasiman, Veynu ^a   Shebanow, Michael ^b   Lee, Chang Joo ^c   Miftakhutdinov, Rustam ^a   Mutlu, Onur ^d   Patt, Yale N ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b NVIDIA   (United States)

^c INTEL CORPORATION   (United States)

^d CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

divergence; GPGPU; SIMD; warp scheduling

Indexed keywords

COMPUTATIONAL POWER; COMPUTATIONAL RESOURCES; CONDITIONAL BRANCH; DIVERGENCE; GENERAL PURPOSE; GPGPU; GPU PROGRAMMING; GRAPHICS PROCESSING UNITS; MICRO ARCHITECTURES; PARALLEL APPLICATION; POPULAR PLATFORM; SIMD;

COMPUTER PROGRAMMING; PROGRAM PROCESSORS; SCHEDULING; SCHEDULING ALGORITHMS;

WEAVING;

EID: 84863342255     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155656     Document Type: Conference Paper

References (27)

1. Advanced Micro Devices, Inc. ATI Stream Technology. http://www.amd.com/ stream.
2. A. Agarwal et al. April: a processor architecture for multiprocessing. In ISCA-17, 1990.
3. B. Amrutur and M. Horowitz. Speed and power scaling of SRAMs. IEEE JSCC, 35(2):175-185, Feb. 2000.
4. W. J. Bouknight et al. The Illiac IV system. Proceedings of the IEEE, 60(4):369-388, Apr. 1972.
5. S. Che et al. Rodinia: A benchmark suite for heterogeneous computing. In IISWC, 2009.
6. W. W. L. Fung and T. Aamodt. Thread block compaction for efficient simt control flow. In HPCA-17, 2011.
7. W. W. L. Fung et al. Dynamic warp formation and scheduling for efficient GPU control flow. In MICRO-40, 2007.
8. W. W. L. Fung et al. Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware. ACM TACO, 6(2):1-37, June 2009.
9. W.-M. Hwu et al. Compute unified device architecture application suitability. Computing in Science Engineering, may-jun 2009.
10. N. Jayasena et al. Stream register files with indexed access. In HPCA-10, 2004.
11. U. Kapasi et al. Efficient conditional operations for data-parallel architectures. In MICRO-33, 2000.
12. B. Khailany et al. Vlsi design and verification of the imagine processor. In ICCD, 2002.
13. Khronos Group. OpenCL. http://www.khronos.org/opencl.
14. D. Kirk and W. W. Hwu. Programming Massively Parallel Processors: A Hands-on Approach. Elsevier Science, 2010.
15. R. Krashinsky et al. The vector-thread architecture. In ISCA-31, 2004.
16. N. B. Lakshminarayana and H. Kim. Effect of instruction fetch and memory scheduling on gpu performance. In Workshop on Language, Compiler, and Architecture Support for GPGPU, 2010.
17. J. Meng et al. Dynamic warp subdivision for integrated branch and memory divergence tolerance. In ISCA-37, 2010.
18. R. Narayanan et al. MineBench: A benchmark suite for data mining workloads. In IISWC, 2006.
19. NVIDIA. CUDA GPU Computing SDK. http://developer.nvidia.com/gpu- computing-sdk.
20. NVIDIA. CUDA Programming Guide Version 3.0, 2010.
21. NVIDIA. PTX ISA Version 2.0, 2010.
22. R. M. Russell. The CRAY-1 computer system. Communications of the ACM, 21(1):63-72, Jan. 1978.
23. S. Ryoo et al. Optimization principles and application performance evaluation of a multithreaded GPU using CUDA. In PPoPP, 2008.
24. B. J. Smith. A pipelined shared resource MIMD computer. In ICPP, 1978.
25. J. E. Smith et al. Vector instruction set support for conditional operations. In ISCA-27, 2000.
26. J. E. Thornton. Parallel operation in the control data 6600. In AFIPS, 1965.
27. D. M. Tullsen and J. A. Brown. Handling long-latency loads in a simultaneous multithreading processor. In MICRO-34, 2001.