Adaptive granularity memory systems: A tradeoff between storage efficiency and throughput

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 295-306

  Yoon, Doe Hyun ^a   Jeong, Min Kyu ^a   Erez, Mattan ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Access granularity; ECC; Main memory

Indexed keywords

ACCESS GRANULARITY; BENCHMARK SUITES; COARSE-GRAINED; ECC; MAIN MEMORY; MEMORY ACCESS; MEMORY SYSTEMS; SPATIAL LOCALITY; STORAGE EFFICIENCY; VIRTUAL MEMORY;

MEMORY ARCHITECTURE; COMMERCE;

CACHE MEMORY;

EID: 80052542940     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000100     Document Type: Conference Paper

References (52)

1. HPC challenge. http://icl.cs.utk.edu/hpcc/hpccfiresults.cgi.
2. HPCS scalable synthetic compact application (SSCA). http://www. highproductivity.org/SSCABmks.htm.
3. Linked list traversal micro-benchmark. http://www-sal.cs.uiuc.edu/ ~zilles/llubenchmark.html.
4. ZFS the last word in file systems. http: //www.opensolaris.org/os/ community/zfs/docs/zfsfilast.pdf.
5. Calculating memory system power for DDR3. Technical Report TN-41-01, Micron Technology, 2007.
6. D. Abts, A. Bataineh, S. Scott, G. Faanes, J. Schwarzmeier, E. Lundberg, M. Byte, and G. Schwoerer. The Cray Black Widow: A highly scalable vector multiprocessor. In Proc. the Int'l Conf. High Performance Computing, Networking, Storage, and Analysis (SC), Nov. 2007.
7. J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber. Future scaling of processor-memmory interfaces. In Proc. the Int'l Conf. High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009.
8. J. H. Ahn, J. Leverich, R. Schreiber, and N. P. Jouppi. Multicore DIMM: An energy efficient memory module with independently controlled DRAMs. IEEE Computer Architecture Letters, 8(1):5-8, Jan.-Jun. 2009.
9. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. Technical Report TR-811-08, Princeton Univ., Jan. 2008.
10. T. M. Brewer. Instruction set innovations for the Convey HC-1 computer. IEEE Micro, 30(2):70-79, 2010.
11. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. the 27th Ann. Int'l Symp. Computer Architecure (ISCA), Jun. 2000.
12. M. C. Carlisle and A. Rogers. Software caching and computation migration in Olden. Technical Report TR-483-95, Princeton University, 1995.
13. C. Chen, S.-H. Yang, B. Falsafi, and A. Moshovos. Accurate and complexity-effective spatial pattern prediction. In Proc. the 10th Int'l Symp. High-Performance Computer Architecture (HPCA), Feb. 2004.
14. C. L. Chen and M. Y. Hsiao. Error-correcting codes for semiconductor memory applications: A state-of-the-art review. IBM J. Research and Development, 28(2):124-134, Mar. 1984.
15. R. Danilak. Transparent error correction code memory system and method. US Patent, US 7,117,421, Oct. 2006.
16. Earl Joseph II. GUPS (giga-updates per second) benchmark. http://www.dgate.org/~brg/files/dis/gups/.
17. S. Eyerman and L. Eeckhout. System-level performance metrics for multiprogram workloads. IEEE Micro, 28(3):42-53, 2008.
18. A. Gonzalez, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In Proc. the Int'l Conf. Supercomputing (ICS), Jul. 1995.
19. M. J. Haertel, R. S. Polzin, A. Kocev, and M. B. Steinman. ECC implementation in non-ECC components. US Patent Pending, Serial No. 725,922, Sep. 2008.
20. G. Hamerly, E. Perelman, J. Lau, and B. Calder. SimPoint 3.0: Faster and more flexible program analysis. In Proc. the Workshop on Modeling, Benchmarking and Simulation (MoBS), Jun. 2005.
21. A. Hilton, N. Eswaran, and A. Roth. FIESTA: A sample-balanced muilti-program workload methodology. In Proc. the Workshop on Modeling, Benchmarking and Simulation (MoBS), Jun. 2009.
22. Intel Corp. Intel RIA-64 and IA-32 Architecture Software Developer's Manual, Mar. 2010.
23. M. K. Jeong, D. H. Yoon, and M. Erez. DrSim: A platform for flexible DRAM system research. http://lph.ece.utexas.edu/public/DrSim.
24. R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd. Power7: IBM's next-generation server processor. IEEE Micro, 30(2):7-15, 2010.
25. S. Kumar and C. Wilkerson. Exploiting spatial locality in data caches using spatial footprints. In Proc. the 25th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 1998.
26. S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proc. the 42nd Ann. IEEE/ACM Int'l Symp Microarchitecture (MICRO), Dec. 2009.
27. S. Lin and D. J. Costello Jr. Error Control Coding: Fundamentals and Applications. Prentice-Hall, Inc., Englewood Cliffs, NJ, 1983.
28. J. S. Liptay. Structural aspects of the system/360 model 85, part II: The cache. IBM Systems Journal, 7:15-21, 1968.
29. G. H. Loh, S. Subramaniam, and Y. Xie. Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. In Proc. the Int'l Symp. Performance Analysis of Software and Systems (ISPASS), Apr. 2009.
30. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. PIN: Building customized program analysis tools with dynamic instrumentation. In Proc. the ACM Conf. Programming Language Design and Implementation (PLDI), Jun. 2005.
31. J. D. McCalpin. STREAM: Sustainable memory bandwidth in high performance computers. http://www.cs.virginia.edu/stream/.
32. Micron Corp. Micron 1 Gb ×4, ×8, ×16, DDR3 SDRAM: MT41J256M4, MT41J128M8, and MT41J64M16, 2006.
33. N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi. CACTI 6.0. Technical report, HP Labs., Apr. 2009.
34. R. C. Murphy and P. M. Kogge. On the memory access patterns of supercoputer applications: Benchmark selection and its implications. IEEE Transactions on Computers, 56(7):937-945, Jul. 2007.
35. O. Mutlu and T. Moscibroda. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In Proc. the 35h Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2008.
36. M. K. Qureshi, M. A. Suleman, and Y. N. Patt. Line distillation: Increasing cache capacity by filtering unused words in cache lines. In Proc. the 13th Int'l Symp. High Performance Computer Architecture (HPCA), Feb. 2007.
37. S. Rixner, W. J. Dally, U. J. Kapasi, P. R. Mattson, and J. D. Owens. Memory access scheduling. In Proc. the 27th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2000.
38. J. B. Rothman and A. J. Smith. The pool of subsectors cache design. In Proc. the 13th Int'l Conf. Supercomputing (ICS), Jun. 1999.
39. B. Schroeder, E. Pinheiro, and W.-D. Weber. DRAM errors in the wild: A large-scale field study. In Proc. the 11th Int'l Joint Conf. Measurement and Modeling of Computer Systems (SIGMETRICS), Jun. 2009.
40. A. Seznec. Decoupled sectored caches: Conciliating low tag implementation cost. In Proc. the 21st Ann. Int'l Symp. Computer Architecture (ISCA), Apr. 1994.
41. S. Somogyi, T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos. Spatial memory streaming. In Proc. the 33rd Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2006.
42. Standard Performance Evaluation Corporation. SPEC CPU 2006. http://www.spec.org/cpu2006/, 2006.
43. A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In Proc. the Int'l Conf. Supercomputing (ICS), Jun. 1999.
44. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob. DRAMsim: A memory-system simulator. SIGARCH Computer Architecture News (CAN), 33:100-107, Sep. 2005.
45. F. A. Ware and C. Hampel. Micro-threaded row and column operations in a DRAM core. In Proc. the first Workshop on Unique Chips and Systems (UCAS), Mar. 2005.
46. F. A. Ware and C. Hampel. Improving power and data efficiency with threaded memory modules. In Proc. the Int'l Conf. Computer Design (ICCD), 2006.
47. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proc. the 22nd Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 1995.
48. D. H. Yoon and M. Erez. Virtualized and flexible ECC for main memory. In Proc. the 15th Int'l. Conf. Architectural Support for Programming Language and Operating Systems (ASPLOS), Mar. 2010.
49. L. Zhang, Z. Fang, M. Parker, B. Mathew, L. Schaelicke, J. Carter, W. Hsieh, and S. McKee. The Impulse memory controller. IEEE Transactions on Computers, Special Issue on Advances in High Performance Memory Systems, 50(11):1117-1132, Nov. 2001.
50. Z. Zhang, Z. Zhu, and X. Zhang. A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. In Proc. the 33rd IEEE/ACM Int'l Symp. Microarchitecture (MICRO), Dec. 2000.
51. H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. In Proc. the 41st IEEE/ACM Int'l Symp. Microarchitecture (MICRO), Nov. 2008.
52. H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. Decoupled DIMM: Building high-bandwidth memory systems using low-speed DRAM devices. In Proc. the 36th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2009.