CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 61-71

  Rhu, Minsoo ^a   Erez, Mattan ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASELINE DESIGN; CONTROL FLOWS; GENERAL PURPOSE; PERFORMANCE EVALUATION; PREDICTION ACCURACY;

COMPUTER ARCHITECTURE; DEGRADATION; PIPELINE CODES; PROGRAM PROCESSORS;

COMPACTION;

EID: 84864855982     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237006     Document Type: Conference Paper

References (31)

1. J. R. Allen, K. Kennedy, C. Porterfield, and J. Warren. Conversion of control dependence to data dependence. In Proceedings of the 10th ACM SIGACTSIGPLAN symposium on Principles of programming languages, POPL '83, pages 177-189, New York, NY, USA, 1983. ACM.
2. AMD Corporation. AMD Radeon HD 6900M Series Specifications, 2010.
3. AMD Corporation. ATI Stream Computing OpenCL Programming Guide, August 2010.
4. A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt. Analyzing CUDA workloads using a detailed GPU simulator. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2009), April 2009.
5. W. Bouknight, S. Denenberg, D. McIntyre, J. Randall, A. Sameh, and D. Slotnick. The Illiac IV System. In Proceedings of the IEEE, volume 60, pages 369-388, April 1972.
6. S. Che, M. Boyer, J. Meng, D. Tarjan, J. Sheaffer, S.- H. Lee, and K. Skadron. Rodinia: A benchmark suite for heterogeneous computing. In IEEE International Symposium on Workload Characterization (IISWC- 2009), October 2009.
7. G. Diamos, B. Ashbaugh, S. Maiyuran, A. Kerr, H. Wu, and S. Yalamanchili. SIMD R e-Convergence At Thread Frontiers. In 44th International Symposium on Microarchitecture (MICRO-44), December 2011.
8. W. W. Fung and T. M. Aamodt. Thread Block Compaction for Efficient SIMT Control Flow. In 17th International Symposium on High Performance Computer Architecture (HPCA-17), February 2011.
9. W.W. Fung, I. Sham, G. Yuan, and T. M. Aamodt. Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. In 40th International Symposium on Microarchitecture (MICRO-40), December 2007.
10. A. Gharaibeh and M. Ripeanu. Size Matters: Space/- Time Tradeoffs to Improve GPGPU Applications Performance. In 2010 International Conference for High Performance Computing, Networking, Storage and Analysis (SC-2010), November 2010.
11. M. Giles. Jacobi iteration for a Laplace discretisation on a 3D structured grid, 2008.
12. M. Giles and S. Xiaoke. Notes on using the NVIDIA 8800 GTX graphics card. http://people.maths.ox.ac.uk/gilesm/hpc/, 2008.
13. P. Harish and P. Narayanan. Accelerating Large Graph Algorithms on the GPU Using CUDA. In High Performance Computing HiPC 2007, volume 4873, pages 197-208. 2007.
14. IMPACT Research Group. The Parboil Benchmark Suite, 2007.
15. Intel Corporation. Intel AVX: New Frontiers in Performance Improvements and Energy Efficiency, May 2009.
16. Intel Corporation. Intel HD Graphics OpenSource Programmer Reference Manual, June 2011.
17. U. Kapasi, W. Dally, S. Rixner, P. Mattson, J. Owens, and B. Khailany. Efficient conditional operations for data-parallel architectures. In 33th International Symposium on Microarchitecture (MICRO-33), December 2000.
18. J. Meng, D. Tarjan, and K. Skadron. Dynamic warp subdivision for intgrated branch and memory divergence tolerance. In 37th International Symposium on Computer Architecture (ISCA-37), 2010.
19. V. Narasiman, C. Lee, M. Shebanow, R. Miftakhutdinov, O. Mutlu, and Y. Patt. Improving GPU Performance via LargeWarps and Two-LevelWarp Scheduling. In 44th International Symposium on Microarchitecture (MICRO-44), December 2011.
20. NVIDIA Corporation. NVIDIA's Next Generation CUDA Compute Architecture: Fermi, 2009.
21. NVIDIA Corporation. NVIDIA CUDA Programming Guide, 2011.
22. NVIDIA Corporation. PTX: Parallel Thread Execution ISA Version 2.3, 2011.
23. NVIDIA Corporation. CUDA C/C++ SDK CODE Samples, 2011.
24. R. M. R ussell. The CR AY-1 computer system. Commun. ACM, 21:63-72, January 1978.
25. M. Schatz, C. Trapnell, A. Delcher, and A. Varshney. High-throughput sequence alignment using graphics processing units. BMC Bioinformatics, 8(1):474, 2007.
26. L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan. Larrabee: A Many-core x86 Architecture for Visual Computing. ACM Trans. Graph., 27:18:1-18:15, August 2008.
27. J. E. Smith, G. Faanes, and R. Sugumar. Vector instruction set support for conditional operations. In 27th International Symposium on Computer Architecture (ISCA-27), 2000.
28. Steven Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann, 1997.
29. D. Tarjan, J. Meng, and K. Skadron. Increasing memory miss tolerance for SIMD cores. In Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC-09), 2009.
30. S. Woop, J. Schmittler, and P. Slusallek. RPU: a programmable ray processing unit for realtime ray tracing. ACM Trans. Graph., 24:434-444, July 2005.
31. H. Wu, G. Diamos, S. Li, and S. Yalamanchili. Characterization and Transformation of Unstructured Control Flow in GPU Applications. In 1st International Workshop on Characterizing Applications for Heterogeneous Exascale Systems, June 2011.