-
1
-
-
84864847681
-
-
HPCS scalable synthetic compact application (SSCA). http://www. highproductivity.org/SSCABmks.htm.
-
-
-
-
3
-
-
56749154795
-
The Cray Black Widow: A highly scalable vector multiprocessor
-
Nov.
-
D. Abts, A. Bataineh, S. Scott, G. Faanes, J. Schwarzmeier, E. Lundberg, M. Byte, and G. Schwoerer. The Cray Black Widow: A highly scalable vector multiprocessor. In Proc. The Int'l Conf. High Performance Computing, Networking, Storage, and Analysis (SC), Nov. 2007.
-
(2007)
Proc. The Int'l Conf. High Performance Computing, Networking, Storage, and Analysis (SC)
-
-
Abts, D.1
Bataineh, A.2
Scott, S.3
Faanes, G.4
Schwarzmeier, J.5
Lundberg, E.6
Byte, M.7
Schwoerer, G.8
-
4
-
-
74049087888
-
Future scaling of processor-memmory interfaces
-
Nov.
-
J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber. Future scaling of processor-memmory interfaces. In Proc. The Int'l Conf. High Performance Computing, Networking,Storage and Analysis (SC), Nov. 2009.
-
(2009)
Proc. The Int'l Conf. High Performance Computing, Networking,Storage and Analysis (SC)
-
-
Ahn, J.H.1
Jouppi, N.P.2
Kozyrakis, C.3
Leverich, J.4
Schreiber, R.S.5
-
5
-
-
67650604446
-
Multicore DIMM: An energy efficient memory module with independently controlled DRAMs
-
Jan. - Jun.
-
J. H. Ahn, J. Leverich, R. Schreiber, and N. P. Jouppi. Multicore DIMM: An energy efficient memory module with independently controlled DRAMs. IEEE Computer Architecture Letters, 8(1):5-8, Jan. - Jun. 2009.
-
(2009)
IEEE Computer Architecture Letters
, vol.8
, Issue.1
, pp. 5-8
-
-
Ahn, J.H.1
Leverich, J.2
Schreiber, R.3
Jouppi, N.P.4
-
6
-
-
85077963574
-
Onyx: A protoype phase-change memory storage array
-
Jun.
-
A. Akel, A. M. Caulfield, T. I. Mollov, R. K. Gupta, and S. Swanson. Onyx: A protoype phase-change memory storage array. In Proc. The 3rd USENIX conference on Hot topicsin storage and file systems (Hot Storage), Jun. 2011.
-
(2011)
Proc. The 3rd USENIX Conference on Hot Topicsin Storage and File Systems (Hot Storage)
-
-
Akel, A.1
Caulfield, A.M.2
Mollov, T.I.3
Gupta, R.K.4
Swanson, S.5
-
7
-
-
51549095074
-
The PARSEC benchmark suite: Characterization and architectural implications
-
Jan.
-
C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. Technical Report TR-811-08, Princeton Univ., Jan. 2008.
-
(2008)
Technical Report TR-811-08, Princeton Univ.
-
-
Bienia, C.1
Kumar, S.2
Singh, J.P.3
Li, K.4
-
8
-
-
77951180817
-
Instruction set innovations for the Convey HC- 1 computer
-
T. M. Brewer. Instruction set innovations for the Convey HC- 1 computer. IEEE Micro, 30(2):70-79, 2010.
-
(2010)
IEEE Micro
, vol.30
, Issue.2
, pp. 70-79
-
-
Brewer, T.M.1
-
13
-
-
47249094055
-
System-level performance metrics for multiprogram workloads
-
S. Eyerman and L. Eeckhout. System-level performance metrics for multiprogram workloads. IEEE Micro, 28(3):42-53, 2008.
-
(2008)
IEEE Micro
, vol.28
, Issue.3
, pp. 42-53
-
-
Eyerman, S.1
Eeckhout, L.2
-
16
-
-
33748874422
-
SimPoint 3.0: Faster and more flexible program analysis
-
Jun.
-
G. Hamerly, E. Perelman, J. Lau, and B. Calder. SimPoint 3.0: Faster and more flexible program analysis. In Proc. The Workshop on Modeling, Benchmarking and Simulation (MoBS), Jun. 2005.
-
(2005)
Proc. The Workshop on Modeling, Benchmarking and Simulation (MoBS)
-
-
Hamerly, G.1
Perelman, E.2
Lau, J.3
Calder, B.4
-
17
-
-
0035187053
-
Exploring the design space of future cmps
-
J. Huh, D. Burger, and S. Keckler. Exploring the design space of future cmps. In Parallel Architectures and Compilation Techniques, 2001. Proceedings. 2001 International Conference on, pages 199 -210, 2001.
-
(2001)
Parallel Architectures and Compilation Techniques, 2001. Proceedings. 2001 International Conference on
, pp. 199-210
-
-
Huh, J.1
Burger, D.2
Keckler, S.3
-
20
-
-
76749146060
-
McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures
-
Dec.
-
S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proc. The 42nd Ann. IEEE/ACM Int'l Symp Microarchitecture (MICRO), Dec. 2009.
-
(2009)
Proc. The 42nd Ann IEEE/ACM Int'l Symp Microarchitecture (MICRO)
-
-
Li, S.1
Ahn, J.H.2
Strong, R.D.3
Brockman, J.B.4
Tullsen, D.M.5
Jouppi, N.P.6
-
21
-
-
70450227674
-
Disaggregated memory for expansion and sharing in blade servers
-
Jun.
-
K. Lim, J. Chang, T. Mudge, P. Ranganathan, S. K. Reinhardt, and T. F. Wenisch. Disaggregated memory for expansion and sharing in blade servers. In Proc. The 36th Int'l Symp. Computer Architecture (ISCA), Jun. 2009.
-
(2009)
Proc. The 36th Int'l Symp. Computer Architecture (ISCA)
-
-
Lim, K.1
Chang, J.2
Mudge, T.3
Ranganathan, P.4
Reinhardt, S.K.5
Wenisch, T.F.6
-
22
-
-
0002388384
-
Structural aspects of the system/360 model 85, part II: The cache
-
J. S. Liptay. Structural aspects of the system/360 model 85, part II: The cache. IBM Systems Journal, 7:15-21, 1968.
-
(1968)
IBM Systems Journal
, vol.7
, pp. 15-21
-
-
Liptay, J.S.1
-
25
-
-
84864847677
-
-
Micron Corp. Micron 1 Gb ×4, ×8, ×16, DDR3 SDRAM: MT41J256M4, MT41J128M8, and MT41J64M16, 2006
-
Micron Corp. Micron 1 Gb ×4, ×8, ×16, DDR3 SDRAM: MT41J256M4, MT41J128M8, and MT41J64M16, 2006.
-
-
-
-
27
-
-
34147112234
-
On the memory accesspatterns of supercoputer applications: Benchmark selection and its implications
-
Jul.
-
R. C. Murphy and P. M. Kogge. On the memory accesspatterns of supercoputer applications: Benchmark selection and its implications. IEEE Transactions on Computers, 56(7):937-945, Jul. 2007.
-
(2007)
IEEE Transactions on Computers
, vol.56
, Issue.7
, pp. 937-945
-
-
Murphy, R.C.1
Kogge, P.M.2
-
30
-
-
0033691565
-
Memory access scheduling
-
Jun.
-
S. Rixner, W. J. Dally, U. J. Kapasi, P. R. Mattson, and J. D. Owens. Memory access scheduling. In Proc. The 27th Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2000.
-
(2000)
Proc. The 27th Ann. Int'l Symp. Computer Architecture (ISCA)
-
-
Rixner, S.1
Dally, W.J.2
Kapasi, U.J.3
Mattson, P.R.4
Owens, J.D.5
-
33
-
-
84864832793
-
Impact and mitigation of DRAM and SRAM soft errors
-
May
-
C. Slayman. Impact and mitigation of DRAM and SRAM soft errors. IEEE SCV Reliability Seminar http://www.ewh.ieee.org/r6/scv/rl/articles/ Soft%20Error%20mitigation.pdf, May 2010.
-
(2010)
IEEE SCV Reliability Seminar
-
-
Slayman, C.1
-
34
-
-
33845894426
-
Spatial memory streaming
-
Jun.
-
S. Somogyi, T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos. Spatial memory streaming. In Proc. The 33rd Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 2006.
-
(2006)
Proc. The 33rd Ann. Int'l Symp. Computer Architecture (ISCA)
-
-
Somogyi, S.1
Wenisch, T.F.2
Ailamaki, A.3
Falsafi, B.4
Moshovos, A.5
-
35
-
-
84864843097
-
-
Standard Performance Evaluation Corporation. SPEC CPU 2006. http://www.spec.org/cpu2006/, 2006.
-
(2006)
-
-
-
36
-
-
84864843099
-
-
Violin Memory Inc. Scalable memory applicance. http://violin-memory.com/ DRAM.
-
-
-
-
39
-
-
0029179077
-
The SPLASH-2 programs: Characterization and methodological considerations
-
Jun.
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proc. The 22nd Ann. Int'l Symp. Computer Architecture (ISCA), Jun. 1995.
-
(1995)
Proc. The 22nd Ann. Int'l Symp. Computer Architecture (ISCA)
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
43
-
-
66749162556
-
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
-
Nov.
-
H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. In Proc. The 41st IEEE/ACM Int'l Symp. Microarchitecture (MICRO), Nov. 2008.
-
(2008)
Proc. The 41st IEEE/ACM Int'l Symp. Microarchitecture (MICRO)
-
-
Zheng, H.1
Lin, J.2
Zhang, Z.3
Gorbatov, E.4
David, H.5
Zhu, Z.6
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