A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM with 2.5 ns bank to bank active time and no bank group restriction

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 107-118

  Oh, Tae Young ^a   Sohn, Young Soo ^a   Bae, Seung Jun ^a   Park, Min Sang ^a   Lim, Ji Hoon ^a   Cho, Yong Ki ^a   Kim, Dae Hyun ^a   Kim, Dong Min ^a   Kim, Hye Ran ^a   Kim, Hyun Joong ^a   Kim, Jin Hyun ^a   Kim, Jin Kook ^a   Kim, Young Sik ^a   Kim, Byeong Cheol ^a   Kwak, Sang Hyup ^a   Lee, Jae Hyung ^a   Lee, Jae Young ^a   Shin, Chang Ho ^a   Yang, Yunseok ^a   Cho, Beom Sig ^a   Bang, Sam Young ^a   Yang, Hyang Ja ^a   Choi, Young Ryeol ^a   Moon, Gil Shin ^a   Park, Cheol Goo ^a   Hwang, Seok Won ^a   Lim, Jeong Don ^a   Park, Kwang Il ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

Active jitter canceller; bank group; bank to bank active time; bitline sense amplifier enable; core cycle; GDDR5; IO sense amplifier auto calibration; low latency VPP generator; page hit rate; replica impedance monitor; skewed logic; tRRD

Indexed keywords

ACTIVE JITTER CANCELLER; BANK GROUP; BANK TO BANK ACTIVE TIME; BIT LINES; CORE CYCLE; GDDR5; HIT RATE; LOW LATENCY; REPLICA IMPEDANCE MONITOR; SENSE AMPLIFIER; SKEWED LOGIC; TRRD;

CALIBRATION; COMPUTER SIMULATION; DATA TRANSFER; JITTER; OCCUPATIONAL RISKS; SIGNAL GENERATORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 78650867466     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2085991     Document Type: Conference Paper

References (9)

1. S.-J. Bae et al., "An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 121-131, Jan. 2008.
2. R. Kho et al., "A 75 nm 7 Gb/s/pin 1 Gb GDDR5 graphics memory device with bandwidth improvement techniques," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 120-133, Jan. 2010.
3. D. Shin et al., "Wide-range fast-lock duty-cycle corrector with offsettolerant duty-cycle detection scheme for 54 nm 7 Gb/s GDDR5 DRAM interface," in 2009 Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 138-139.
4. K.-I. Oh, L.-S. Kim, K.-I. Park, Y.-H. Jun, J. S. Choi, and K. Kim, "A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme," IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2222-2232, Aug. 2009.
5. K.-S. Ha et al., "A 0.13 μm CMOS 6 Gb/s/pin memory transceiver using pseudo-differential signaling for removing common-mode noise due to SSN," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3146-3162, Nov. 2009.
6. J. Zhu, P. Liu, and D. Zhou, "An SDRAM controller optimized for high definition video coding application," in Proc. 2008 IEEE Int. Symp. Circuits and Systems (ISCAS), May 2008, pp. 3518-3521.
7. H. Yoon et al., "A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM," IEEE J. Solid-State Circuits, vol. 34, no. 11, pp. 1589-1599, Nov. 1999.
8. E. Seevinck, P. J. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 525-536, Apr. 1991.
9. T. Tanzawa and S. Atsumi, "Optimization of word-line booster circuits for low-voltage flash memories," IEEE J. Solid-State Circuits, vol. 34, no. 8, pp. 1091-1098, Aug. 1999.