Mini-rank: Adaptive DRAM architecture for improving memory power efficiency

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 210-221

  Zheng, Hongzhong ^a   Lin, Jiang ^b   Zhang, Zhao ^b   Gorbatov, Eugene ^a   David, Howard ^a   Zhu, Zhichun ^c  

^a UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

^b Iowa State University of Science and Technology   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUS PROTOCOL; FOUR-CORE; HIGH MEMORY BANDWIDTH; MEMORY ACCESS; MEMORY CAPACITY; MULTI-CORE PROCESSOR; PERFORMANCE PENALTIES; PERFORMANCE TRADE-OFF; POWER CONSUMPTION; POWER EFFICIENCY; SUBSYSTEM DESIGN;

ELECTRIC POWER UTILIZATION; MULTIPROGRAMMING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 66749162556     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771792     Document Type: Conference Paper

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