Dynamic warp subdivision for integrated branch and memory divergence tolerance

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 235-246

  Meng, Jiayuan ^a   Tarjan, David ^a   Skadron, Kevin ^a  

^a University of Virginia   (United States)

Author keywords

Branch divergence; Latency hiding; Memory divergence; SIMD; Warp

Indexed keywords

AREA OVERHEAD; CACHE HIERARCHIES; DATA PARALLEL; IDLE CYCLES; L2 CACHE; LATENCY HIDING; MAXIMIZE THROUGHPUT; MEMORY ACCESS; MEMORY LEVEL PARALLELISMS; MULTI-THREADING; MULTIPLE PROCESSING; REGISTER FILES;

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTERS; PROGRAM PROCESSORS; SCHEDULING;

WEAVING;

EID: 77954976292     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1815992     Document Type: Conference Paper

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