Increasing memory miss tolerance for SIMD cores

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09

Volumn , Issue , 2009, Pages

  Tarjan, David ^a,b   Meng, Jiayuan ^a   Skadron, Kevin ^a  

^a University of Virginia   (United States)

^b NVIDIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MANY-CORE; MEMORY ACCESS PATTERNS; MEMORY LATENCIES;

COMPUTER ARCHITECTURE;

WEAVING;

EID: 74049151553     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1654059.1654082     Document Type: Conference Paper

References (26)

1. Intel Advanced Vector Extensions Programming Reference, 2009. http://software.intel.com/file/21558.
2. K. Aingaran, P. Kongetira, and K. Olukotun. Niagara: A 32-way Multithreaded Sparc Processor. IEEE Micro, 25:21-29, 2005.
3. AMD. ATI CTM Guide: Technical reference manual. Technical report, AMD, 2006. Version 1.01.
4. AMD. ATI Radeon HD 2900 Technology, GPU Specifications, 2007.
5. J. A. Anderson, C. D. Lorenz, and A. Travesset. General Purpose Molecular Dynamics Simulations fully implemented on Graphics Processing Units. J. of Computational Physics, 227(10):5342-5359, 2008.
6. R. D. Barnes, E. M. Nystrom, J. W. Sias, S. J. Patel, N. Navarro, and W.-m. W. Hwu. Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. In Proc. 36th IEEE/ACM Int'l Symp. Microarchitecture (MICRO '03), pages 387-398, 2003.
7. L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A Scalable Architecture based on Single-Chip Multiprocessing. In Proc. 27th Int'l Symp. Computer Architecture (ISCA '00), pages 282-293, 2000.
8. D. Blythe. The Direct3D 10 system. ACM Trans. Graphics, 25(3):724-734, 2006.
9. M. Boyer, D. Tarjan, S. T. Acton, and K. Skadron. Accelerating Leukocyte Tracking using CUDA: A Case Study in Leveraging Manycore Coprocessors. In Proc. 24th Int'l Parallel and Distributed Processing Symp. (IPDPS '09), pages 1-12, 2009.
10. I. Buck, T. Foley, D. Horn, J. Sugerman, K. Fatahalian, M. Houston, and P. Hanrahan. Brook for GPUs: Stream Computing on Graphics Hardware. ACM Trans. on Graphics, 23(3):777-786, 2004.
11. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron. A Performance Study of General-Purpose Applications on Graphics Processors using CUDA. J. of Parallel and Distributed Computing, 68(10):1370-1380, 2008.
12. W. J. Dally, F. Labonte, A. Das, P. Hanrahan, J.-H. Ahn, J. Gummaraju, M. Erez, N. Jayasena, I. Buck, T. J. Knight, and U. J. Kapasi. Merrimac: Supercomputing with Streams. In Proc. 15th ACM/IEEE Conf. Supercomputing (SC '03), page 35, 2003.
13. B. K. Flachs, S. Asano, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. S. Liberty, B. W. Michael, H.-J. Oh, S. M. Müller, O. Takahashi, K. Hirairi, A. Kawasumi, H. Murakami, H. Noro, S. Onishi, J. Pille, J. Silberman, S. Yong, A. Hatakeyama, Y. Watanabe, N. Yano, D. A. Brokenshire, M. Peyravian, V. To, and E. Iwata. Microarchitecture and Implementation of the Synergistic Processor in 65-nm and 90-nm SOI. IBM J. Research and Development, 51(5):529-544, 2007.
14. W. W. L. Fung, I. Sham, G. Yuan, and T. M. Aamodt. Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. In Proc. 40th IEEE/ACM Int'l Symp. Microarchitecture (MICRO '07), pages 407-420, 2007.
15. M. Garland, S. L. Grand, J. Nickolls, J. Anderson, J. Hardwick, S. Morton, E. Phillips, Y. Zhang, and V. Volkov. Parallel Computing Experiences with CUDA. IEEE Micro, 28(4):13-27, 2008.
16. A. Glew. MLP yes! ILP no! In ASPLOS Wild and Crazy Ideas, 1998.
17. E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym. NVIDIA Tesla: A Unified Graphics and Computing Architecture. IEEE Micro, 28(2):39-55, 2008.
18. G. H. Loh. The Cost of Uncore in Throughput-Oriented Many-Core Processors. In Workshop on Architectures and Languages for Throughput Applications, 2008.
19. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. In "Proc. 9th Int'l Conf. High Performance Computer Architecture (HPCA '03)", pages 129-140, 2003.
20. R. Narayanan, B. Ozisikyilmaz, J. Zambreno, G. Memik, and A. Choudhary. MineBench: A Benchmark Suite for Data Mining Workloads. In Proc. 2006 IEEE Int'l Symposium on Workload Characterization (ISWC '06), pages 182-188, 2006.
21. J. Nickolls, I. Buck, M. Garland, and K. Skadron. Scalable Parallel Programming with CUDA. ACM Queue, 6(2):40-53, 2008.
22. K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The Case for a Single-Chip Multiprocessor. In Proc. 7th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), pages 2-11, 1996.
23. M. Raab, L. Grünschloss, J. Hanikaz, M. Finckh, and A. Keller. bwfirt. http://bwfirt.sourceforge.net/.
24. M. Schatz, C. Trapnell, A. Delcher, and A. Varshney. High-Throughput Sequence Alignment using Graphics Processing Units. BMC Bioinformatics, 8(1):474, 2007.
25. L. Seiler et al. Larrabee: A Many-Core x86 Architecture for Visual Computing. ACM Trans. on Graphics, 27(3):1-15, 2008.
26. S. T. Srinivasan, R. Rajwar, H. Akkary, A. Gandhi, and M. Upton. Continual Flow Pipelines. In Proc. 11th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), pages 107-119, 2004.