Future scaling of processor-memory interfaces

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09

Volumn , Issue , 2009, Pages

  Ahn, Jung Ho ^a   Jouppi, Norman P ^a   Kozyrakis, Christos ^b   Leverich, Jacob ^b   Schreiber, Robert S ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSOR; DRAM DEVICES; GLOBAL WIRES; HIGH BANDWIDTH; HIGH-RELIABILITY SYSTEMS; IN-PROCESS TECHNOLOGY; MAIN-MEMORY; MEMORY SYSTEMS; MULTI CORE; MULTITHREADED; PROCESSOR PERFORMANCE; PROCESSOR-MEMORY; SOFT ERROR; SYSTEM LEVELS;

ERROR CORRECTION; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; RELIABILITY; SYSTEMS ANALYSIS; WIRELESS TELECOMMUNICATION SYSTEMS;

ENERGY EFFICIENCY;

EID: 74049087888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1654059.1654102     Document Type: Conference Paper

References (37)

1. "Calculating Memory System Power for DDR3," Micron, Tech. Rep. TN-41-01, 2007.
2. J. Ahn, J. Leverich, R. S. Schreiber, and N. P. Jouppi, "Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs," Computer Architecture Letters, vol. 7, no. 1, 2008.
3. AMD, BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors, Jul 2007, http://www. amd.com/us-en/assets/content-type/white- papers-and-tech-docs/32559.pdf.
4. L. A. Barroso, "The price of performance," Queue, vol. 3, no. 7, pp. 48-53, 2005.
5. C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The PARSEC Benchmark Suite: Characterization and Architectural Implications," in PACT, Oct 2008.
6. T. J. Dell, "A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory," IBM Microelectronics Division, Nov. 1997.
7. J. M. Frailong, W. Jalby, and J. Lenfant, "XOR-Schemes: A Flexible Data Organization in Parallel Memories," in ICPP, Aug 1985.
8. J. Gee, M. D. Hill, D. N. Pnevmatikatos, and A. J. Smith, "Cache Performance of the SPEC92 Benchmark Suite," IEEE Micro, vol. 13, 1993.
9. M. Ghosh and H.-H. S. Lee, "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs," in MICRO, Dec 2007.
10. J. L. Henning, "Performance counters and development of SPEC CPU2006," Computer Architecture News, vol. 35, no. 1, 2007.
11. R. Ho, K. Mai, and M. A. Horowitz, "The Future of Wires," Proceedings of the IEEE, vol. 89, no. 4, 2001.
12. H. Huang, P. Pillai, and K. G. Shin, "Design and Implementation of Power-Aware Virtual Memory," in USENIX, Jun 2003.
13. I. Hur and C. Lin, "A Comprehensive Approach to DRAM Power Management," in HPCA, Feb 2008.
14. Intel, "Intel® Core™ i7 Processor, http://www.intel.com/ products/processor/corei7/."
15. B. Jacob, S. W. Ng, and D. T. Wang, Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, 2007.
16. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, 2005.
17. A. R. Lebeck, X. Fan, H. Zeng, and C. Ellis, "Power Aware Page Allocation," in ASPLOS, Nov 2000.
18. A. Leon, B. Langley, and J. L. Shin, "The UltraSPARC T1 Processor: CMT Reliability," CICC, Sep 2006.
19. C.-K. Luk, et al., "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," in PLDI, Jun 2005.
20. M. M. K. Martin, et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Computer Architecture News, vol. 33, no. 4, 2005.
21. B. K. Mathew, S. A. Mckee, J. B. Carter, and A. Davis, "Design of a Parallel Vector Access Unit for SDRAM Memory Systems," in HPCA, Jan 2000.
22. H. McGhan, "SPEC CPU2006 Benchmark Suite," in Microprocessor Report, Oct 2006.
23. Micron Technology Inc., DDR2 SDRAM Datasheet, 2008, http://www.micron.com/products/dram/ddr2/.
24. -, DDR3 SDRAM Datasheet, 2008, http://www.micron.com/products/ dram/ddr3/.
25. -, RLDRAM Datasheet, 2008, http://www.micron.com/products/dram/ rldram/.
26. O. Mutlu and T. Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors," in MICRO, Dec 2007.
27. K. J. Nesbit, N. Aggarwal, J. Laudon, and J. E. Smith, "Fair Queuing Memory Systems," in MICRO, Dec 2006.
28. H. Pan, K. Asanović, R. Cohn, and C.-K. Luk, "Controlling Program Execution through Binary Instrumentation," SIGARCH Computer Architecture News, vol. 33, no. 5, 2005.
29. W. W. Peterson and J. E. J. Weldon, Error-Correctin Codes, 2nd ed. MIT Press, 1972.
30. Rambus, "RDRAM, http://www.rambus.com," 1999.
31. S. H. Reiger, "Codes for the Correction of "Clustered" Errors," in IRE Transactions on Information Theory, 1960.
32. S. Rixner, W. J. Dally, U. J. Kapasi, P. R. Mattson, and J. D. Owens, "Memory Access Scheduling," in ISCA, Jun 2000.
33. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, "Automatically Characterizing Large Scale Program Behavior," in ASPLOS, Oct 2002.
34. S. Thoziyoor, J. Ahn, M. Monchiero, J. B. Brockman, and N. P. Jouppi, "A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies," in ISCA, Jun 2008.
35. F. A. Ware and C. Hampel, "Improving Power and Data Efficiency with Threaded Memory Modules," in ICCD, Oct 2006.
36. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations," in ISCA, Jun 1995.
37. H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu, "Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency," in Micro, Nov 2008.