Modeling and characterization of gate leakage in high-K metal gate technology-Based embedded DRAM

IEEE Transactions on Electron Devices

Volumn 60, Issue 12, 2013, Pages 4152-4158

  Bajaj, Mohit ^a   Pandey, Rajan K ^a   De, Sandip ^a   Sathaye, Ninad D ^a   Jayaraman, Balaji ^a   Krishnan, Rishikesh ^b   Goyal, Puneet ^a   Furkay, Stephen S ^c   Nowak, Edward J ^c   Iyer, Subramanian S ^b   Murali, Kota V R M ^a  

^a IBM RESEARCH INDIA   (India)

^b IBM   (United States)

^c IBM RESEARCH   (United States)

Author keywords

Deep trench (DT) capacitor; Direct tunneling; Embedded dynamic random access memory (eDRAM); High K metal gate (HKMG); Trap assisted tunneling (TAT)

Indexed keywords

DEEP TRENCH; DIRECT TUNNELING; EMBEDDED DYNAMIC RANDOM ACCESS MEMORY; HIGH-K METAL GATES; TRAP ASSISTED TUNNELING;

FINITE ELEMENT METHOD; HAFNIUM OXIDES;

CAPACITORS;

EID: 84889655720     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2013.2285940     Document Type: Article

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