Characterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2010, Pages

  Goyal, P ^a   Gupta, S ^a   Krishnan, R ^b   Davies, W ^b   Ho, H ^b   Tessier, A ^b   Arya, A ^b   Deshpande, S ^b   Fang, S ^b   Lee, S ^b   Li, Z ^a,b   Liu, J ^b   Takalkar, R ^b   Dadson, J ^b   Chakravarti, A ^b   Domenicucci, A ^b   Shepard, J ^b   McStay, K ^b   Morgenfeld, B ^b   Allen, S ^b   Li, X ^b   Khan, B ^b   Knarr, R ^b   Arndt, R ^b   Venigalla, R ^b   Parries, P ^b   Chudzik, M ^b   Stiffler, S ^b   more..

^a IBM RESEARCH INDIA   (India)

^b IBM RESEARCH   (United States)

Author keywords

Capacitance; Capacitor; Deep trench (DT); eDRAM; HfO2; Leakage; TiN

Indexed keywords

DEEP TRENCH; EDRAM; END-OF-LINE; FULLY COMPATIBLE; HFO2; LEAKAGE; LEAKAGE MECHANISM; METAL ELECTRODE MATERIALS; METAL FILM; METAL-INSULATOR-SEMICONDUCTORS; MITIGATION TECHNIQUES; RANDOM VARIATION; SOURCES OF VARIATION; THERMAL BUDGET; TRENCH CAPACITORS;

CAPACITANCE; ELECTROLYTIC CAPACITORS; HAFNIUM COMPOUNDS; METAL INSULATOR BOUNDARIES; MIS DEVICES; TITANIUM NITRIDE;

CAPACITORS;

EID: 78650556086     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2010.5641378     Document Type: Conference Paper

References (4)

1. G. Wang et al, "A 0.127 μm2 high performance 65nm SOI based embedded DRAM for on-processor applications" IEDM, Dec 2006
2. P. Klim et al, "A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS", VLSI Tech Symp, June 2008
3. G.Wang et al, "Scaling deep trench based eDRAM on SOI to 32nm and beyond", IEDM 2009
4. 2", Microelectronics and Reliability Journal, Vol 45, Issue 5-6, June 2005.