Measurement and analysis of thermal stresses in 3D integrated structures containing through-silicon-vias

Microelectronics Reliability

Volumn 53, Issue 1, 2013, Pages 53-62

  Jiang, Tengfei ^a   Ryu, Suk Kyu ^a   Zhao, Qiu ^a   Im, Jay ^a   Huang, Rui ^a   Ho, Paul S ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

32 NM TECHNOLOGY; 3D STRUCTURES; DEFORMATION AND STRESS; DEFORMATION MECHANISM; ELASTIC ANISOTROPY; EXPERIMENTAL MEASUREMENTS; EXPERIMENTAL OBSERVATION; INTEGRATED STRUCTURE; MEASUREMENT AND ANALYSIS; MICRO RAMAN SPECTROSCOPY; MOBILITY DEGRADATION; THREEDIMENSIONAL (3-D); THROUGH SILICON VIAS; WAFER CURVATURE TECHNIQUE;

DEFORMATION; EXTRUSION; FINITE ELEMENT METHOD; LOGIC DEVICES; RAMAN SPECTROSCOPY; SILICON; SILICON WAFERS; THERMAL EXPANSION;

THERMAL STRESS;

EID: 84872106383     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2012.05.008     Document Type: Article

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