Stress-induced delamination of through silicon via structures

AIP Conference Proceedings

Volumn 1378, Issue , 2011, Pages 153-167

  Ryu, Suk Kyu ^a   Lu, Kuan Hsun ^a   Im, Jay ^a   Huang, Rui ^a   Ho, Paul S ^a  

^a The University of Texas at Austin   (United States)

Author keywords

3D interconnect; Crack driving force; FEA; Thermo mechanical reliability; TSV

Indexed keywords

EID: 80053653482     PISSN: 0094243X     EISSN: 15517616     Source Type: Conference Proceeding    
DOI: 10.1063/1.3615702     Document Type: Conference Paper

References (26)

1. International Technology Roadmap for Semiconductors (ITRS), 2009.
2. M.S. Bakir and J.D. Meindl, Integrated interconnect technologies for 3D nanoelectronic systems. Artech House, Norwood, MA, 2009.
3. J.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, M.J. Interrante, C.S. Patel, R.J. Polastre, K. Sakuma, R. Sirdeshmukh, E.J. Sprogis, S.M. Sri-Jayantha, A.M. Stephens, A.W. Topol, C.K. Tsang, B.C. Webb and S.L. Wright, Three-dimensional silicon integration, IBM J. Res. & Dev. 52, 553-569 (2008).
4. J. Lu, 3-D hyperintegration and packaging technologies for micro-nano systems, Proc. IEEE 97, 18-30 (2009).
5. L.W. Schaper, S.L. Burkett, S. Spiesshoefer, G.V. Vangara, Z. Rahman and S. Polamreddy, Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias, IEEE Trans. Advanced Packaging 28, 356-366 (2005).
6. K. Sakuma, P.S. Andry, C.K. Tsang, S.L. Wright, B. Dang, C.S. Patel, B.C. Webb, J. Maria, E.J. Sprogis, S.K. Kang, R.J. Polastre, R.R. Horton and J.U. Knickerbocker, 3D chip-stacking technology with through-silicon vias and low-volume leadfree interconnections, IBM J. RES. & DEV. 52, 611-622 (2008).
7. K. Sakumar, N. Nagai, M. Saito, J. Mizuno and S. Shoji, Simplified 20-μm pitch vertical interconnection process for 3D chip stacking, IEEJ Trans. on Electrical and Electronic Engineering 4, 339-344 (2009).
8. S. Thompson, G. Sun, Y. Choi and T. Nishida, Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap, IEEE Trans. On Electron Devices 53, 1010-1020 (2006).
9. A.P. Karmarker, X. Xu and V. Moroz, Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV), Proc. IEEE 47th Annual International Reliability Physics Symposium, Montreal, 2009, pp. 682-687.
10. C.S. Selvanayagam, J.H. Lau, X. Zhang, S.K.W. Seah, K. Vaidyanathan and T.C. Chai, Nonlinear thermal stress/strain analyses of copper filled TSV (Through Silicon Via) and their flip-chip microbumps, Electronic Components and Technology Conference, 2008, pp. 1073-1081.
11. N. Ranganathan, K. Prasad, N. Balasubramanian and K.L. Pey, A study of thermo-mechanical stress and its impact on through-silicon vias, J. Micromech. Microeng. 18, 1-13 (2008).
12. X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. Tummala and S. Sitaraman, Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV), Electronic Components and Technology Conference, 2009, pp. 624-629.
13. K. Lu, X. Zhang, S. Ryu, J. Im, R. Huang and P. Ho, Thermo-mechanical reliability of 3-D ICs containing through-silicon-vias, Electronic Components and Technology Conference, 2009, pp. 630-634.
14. K. Lu, X. Zhang, S. Ryu, R. Huang and P. Ho, Thermal stresses analysis of 3-D interconnect, 10th International Workshop on Stress-Induced Phenomena in metallization, Proc. American Institute of Physics Conference 1143, 2009, pp. 224-230.
15. A.E.H. Love, The stress produced in a semi-infinite solid by pressure on part of the boundary, Philos. Trans. A 228, 377-420 (1929).
16. T.C. Lu, J. Yang, Z. Suo, A.G. Evans, R. Hecht and R.Mehrabian, Matrix cracking in intermetallic composites caused by thermal expansion mismatch, ACTA Metall. Mater. 39, 1883-1890 (1991).
17. S. Ryu, K. Lu, X. Zhang, J. Im, P. Ho and R. Huang, IEEE Trans. TDMR, 2010.DOI:10.1109/TDMR.2010.2068572.
18. M.W. Lane, R.H. Dauskardt, N. Krishna and I. Hashim, Adhesion and reliability of copper interconnects with Ta and TaN barrier layers, J. Mater. Res. 15, 203-211 (2000).
19. M. Lane, A. Vainchtein, H. Gao and R.H. Dauskardt, Plasticity contributions to interface adhesion in thin-film interconnect structures, J. Mater. Res. 15, 2758-2769 (2000).
20. O. Luhn, C.V. Hoof, W. Ruythooren and J. Celis, Barrier and seed layer coverage in 3D structures with different aspect ratios using sputtering and ALD processes, Microelectronic Engineering 85, 1947-1951 (2008).
21. G. Druais, G. Dilliway, P. Fischer, E. Guidotti, A. Radisic and S. Zahraoui, High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed, Microelectronic Engineering 85, 1957-1961 (2008).
22. S. Lee, R. Hon, S. Zhang and C. Wong, 3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling, Electronic Components and Technology Conference, 2005, pp. 795-801.
23. M.W. Lane, R.H. Dauskardt, N. Krishna and I. Hashim, "Adhesion and reliability of copper interconnects with Ta and TaN barrier layers", J. Mater. Res. 15, 203-211 (2000).
24. B. Majeed, N. Pham, D. Tezcan and E. Beyne, Parylene N as a dielectric material for through silicon vias, Electronic Components and Technology Conference, 2008, pp. 1556-1561.
25. D. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan and B. Swinnen, Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging, Electronic Components and Technology Conference, 2009, pp. 1159-1164.
26. J. Im, E.O. II, J. Theodore Stokich, A. Strandjord, J. Hetzner, J. Curphy and C. Karas, On the mechanical reliability of photo-BCB-based thin film dielectric polymer for electronic packaging applications, J. Electronic Packaging 122, 28-33 (2000).