Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D Interconnects

IEEE Transactions on Device and Materials Reliability

Volumn 11, Issue 1, 2011, Pages 35-43

  Ryu, Suk Kyu ^a   Lu, Kuan Hsun ^a   Zhang, Xuefeng ^b   Im, Jang Hi ^a   Ho, Paul S ^a   Huang, Rui ^a  

^a The University of Texas at Austin   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

3 D interconnects; Interfacial delamination; thermal stress; through silicon via (TSV)

Indexed keywords

3-D INTEGRATION; 3-D INTERCONNECTS; ANALYTICAL SOLUTIONS; CRACK LENGTH; DIE STACKING; DIELECTRIC BUFFERS; DRIVING FORCES; EFFECTIVE SOLUTION; FAILURE MECHANISM; FINITE ELEMENT ANALYSIS; INTERFACIAL DELAMINATION; INTERFACIAL FRACTURE; INTERFACIAL RELIABILITY; LINEAR SUPERPOSITIONS; MATERIAL PROPERTY; MATERIALS AND PROCESS; NEAR-SURFACE; NUMERICAL RESULTS; ON-CHIP WIRING; STEADY-STATE ENERGIES; TECHNOLOGY NODES; THERMALLY INDUCED STRESS; THERMOMECHANICAL RELIABILITY; THROUGH SILICON VIAS; THROUGH-SILICON VIA (TSV); UPPER BOUND; WAFER SURFACE; WAFER THICKNESS;

DELAMINATION; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; MICROELECTRONICS; QUALITY ASSURANCE; RELIABILITY; SILICON WAFERS; STEEL SHEET; STRESS ANALYSIS; THERMAL STRESS; THERMOELASTICITY; THREE DIMENSIONAL;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 79952820386     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2010.2068572     Document Type: Article

References (28)

1. International Technology Roadmap for Semiconductors (ITRS), 2009.
2. M. S. Bakir and J. D. Meindl, Integrated Interconnect Technologies for 3D Nanoelectronic Systems. Norwood, MA: Artech House, 2009.
3. J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, "Three-dimensional silicon integration," IBM J. Res. Develop., vol. 52, no. 6, pp. 553-569, Nov. 2008.
4. J.-Q. Lu, "3-D hyperintegration and packaging technologies for micronano systems," Proc. IEEE, vol. 97, no. 1, pp. 18-30, Jan. 2009.
5. L. W. Schaper, S. L. Burkett, S. Spiesshoefer, G. V. Vangara, Z. Rahman, and S. Polamreddy, "Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias," IEEE Trans. Adv. Packag., vol. 28, no. 3, pp. 356-366, Aug. 2005. (Pubitemid 41263741)
6. K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E. J. Sprogis, S. K. Kang, R. J. Polastre, R. R. Horton, and J. U. Knickerbocker, "3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections," IBM J. Res. Develop., vol. 52, no. 6, pp. 611-622, Nov. 2008.
7. K. Sakuma, N. Nagai, M. Saito, J. Mizuno, and S. Shoji, "Simplified 20-μm pitch vertical interconnection process for 3D chip stacking," IEEJ Trans. Elect. Electron. Eng., vol. 4, no. 3, pp. 339-344, May 2009.
8. S. E. Thompson, G. Sun, Y. Choi, and T. Nishida, "Uniaxial- processinduced strained-Si: Extending the CMOS roadmap," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.
9. A. P. Karmarker, X. Xu, and V.Moroz, "Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV)," in Proc. IEEE 47th Annu. Int. Reliab. Phys. Symp., Montreal, QC, Canada, 2009, pp. 682-687.
10. C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K.W. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps," in Proc. ECTC, 2008, pp. 1073-1081.
11. N. Ranganathan, K. Prasad, N. Balasubramanian, and K. L. Pey, "A study of thermo-mechanical stress and its impact on through-silicon vias," J. Micromech. Microeng., vol. 18, no. 7, p. 075 018, Jun. 2008.
12. X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. Tummala, and S. Sitaraman, "Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV)," in Proc. ECTC, 2009, pp. 624-629.
13. K. Lu, X. Zhang, S. Ryu, J. Im, R. Huang, and P. S. Ho, "Thermomechanical reliability of 3-D ICs containing through silicon vias," in Proc. ECTC, 2009, pp. 630-634.
14. K. Lu, X. Zhang, S. Ryu, R. Huang, and P. S. Ho, "Thermal stresses analysis of 3-D interconnect," in Proc. 10th Int. Workshop Stress-Induced PhenomenaMetallization, vol. 1143, AIP Conference, 2009, pp. 224-230.
15. T. C. Lu, J. Yang, Z. Suo, A. G. Evans, and R. Hecht, "Matrix cracking in intermetallic composites caused by thermal expansion mismatch," Acta Metall. Mater., vol. 39, no. 8, pp. 1883-1890, Aug. 1991. (Pubitemid 21680073)
16. S. Timoshenko and J. N. Goodier, Theory of Elasticity. New York: McGraw-Hill, 1970, pp. 403-407.
17. A. E. H. Love, "The stress produced in a semi-infinite solid by pressure on part of the boundary," Philos. Trans. Roy. Soc. London A, Math. Phys. Sci., vol. 228, pp. 377-420, 1929.
18. A. Horwitz, "A version of Simpson's rule for multiple integrals," J. Comput. Appl. Math., vol. 134, no. 1/2, pp. 1-11, Sep. 2001. (Pubitemid 32836214)
19. R. E. Geer, "Profiling of process-induced stress in Cu through-silicon vias (TSVs) for wafer-scale, 3D integration," in Proc. 11th Int. Workshop Stress-Induced PhenomenaMetallization, Dresden, Germany, Apr. 12-14, 2010.
20. M. W. Lane, R. H. Dauskardt, N. Krishna, and I. Hashim, "Adhesion and reliability of copper interconnects with Ta and TaN barrier layers," J. Mater. Res., vol. 15, no. 1, pp. 203-211, Jan. 2000. (Pubitemid 34566550)
21. M. W. Lane, A. Vainchtein, H. Gao, and R. H. Dauskardt, "Plasticity contributions to interface adhesion in thin-film interconnect structures," J. Mater. Res., vol. 15, no. 12, pp. 2758-2769, Dec. 2000. (Pubitemid 34567086)
22. O. Luhn, C. V. Hoof,W. Ruythooren, and J. Celis, "Barrier and seed layer coverage in 3D structures with different aspect ratios using sputtering and ALD processes," Microelectron. Eng., vol. 85, no. 10, pp. 1947-1951, Oct. 2008.
23. G. Druais, G. Dilliway, P. Fischer, E. Guidotti, A. Radisic, and S. Zahraoui, "High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed," Microelectron. Eng., vol. 85, no. 10, pp. 1957-1961, Oct. 2008.
24. S. Lee, R. Hon, S. Zhang, and C. Wong, "3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling," in Proc. ECTC, 2005, pp. 795-801. (Pubitemid 41276268)
25. B. Majeed, N. Pham, D. Tezcan, and E. Beyne, "Parylene N as a dielectric material for through silicon vias," in Proc. ECTC, 2008, pp. 1556-1561.
26. D. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan, and B. Swinnen, "Scalable through silicon via with polymer deep trench isolation for 3D wafer level packaging," in Proc. ECTC, 2009, pp. 1159-1164.
27. H. Mei, Y. Pang, and R. Huang, "Influence of interfacial delamination on channel cracking of elastic thin films," Int. J. Fract., vol. 148, no. 4, pp. 331-342, 2007.
28. J. Im, E. O. , II, J. Theodore Stokich, A. Strandjord, J. Hetzner, J. Curphy, and C. Karas, "On the mechanical reliability of photo-BCB-based thin film dielectric polymer for electronic packaging applications," J. Electron. Packag., vol. 122, no. 1, pp. 28-33, Mar. 2000.