Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3-D integration

IEEE Transactions on Device and Materials Reliability

Volumn 12, Issue 2, 2012, Pages 255-262

  Ryu, Suk Kyu ^a   Lu, Kuan Hsun ^a   Jiang, Tengfei ^a   Im, Jang Hi ^a   Huang, Rui ^a   Ho, Paul S ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Finite element analysis (FEA); keep out zone (KOZ); thermomechanical reliability; three dimensional interconnects; through silicon via (TSV)

Indexed keywords

3-D INTEGRATION; [110] DIRECTION; DEVICE PERFORMANCE; EFFECT OF STRESS; EFFECTIVE SOLUTION; ELASTIC ANISOTROPY; ELECTRONIC DEVICE; KEEP-OUT ZONE (KOZ); NEAR-SURFACE STRESS; P-TYPE SI; PIEZORESISTIVITY; SI SURFACES; STRESS EFFECTS; STRESS INTERACTION; STRESS LEVELS; THERMOMECHANICAL RELIABILITY; THREEDIMENSIONAL (3-D); THROUGH SILICON VIAS; THROUGH-SILICON VIA (TSV);

ALIGNMENT; ELECTRON DEVICES; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; PLASTICITY; SILICON; THERMAL STRESS; THREE DIMENSIONAL;

CARRIER MOBILITY;

EID: 84862024348     PISSN: 15304388     EISSN: 15582574     Source Type: Journal    
DOI: 10.1109/TDMR.2012.2194784     Document Type: Article

References (27)

1. M. S. Bakir and J. D. Meindl, Integrated Interconnect Technologies for 3D Nanoelectronic Systems. Norwood, MA: Artech House, 2009.
2. J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, "Three-dimensional silicon integration," IBM J. Res. Develop., vol. 52, no. 6, pp. 553-569, Nov. 2008.
3. J.-Q. Lu, "3-D hyperintegration and packaging technologies for micronano systems," Proc. IEEE, vol. 97, no. 1, pp. 18-30, Jan. 2009.
4. S.K. Ryu, T. Jiang, K. H. Lu, J. Im, H.-Y. Son, K.-Y. Byun, R. Huang, and P. Ho, "Characterization of thermal stresses in through-silicon vias by bending beam technique," Appl. Phys. Lett., vol. 100, no. 4, p. 041901, Jan. 2012.
5. S.K. Ryu, Q. Zhao, M. Hecker, H.-Y. Son, K.-Y. Byun, J. Im, P. Ho, and R. Huang, "Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects," J. Appl. Phys., vol. 111, no. 6, pp. 063513-1-063513-8, Mar. 2012.
6. C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K.W. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps," in Proc. ECTC, 2008, pp. 1073-1081.
7. N. Ranganathan, K. Prasad, N. Balasubramanian, and K. L. Pey, "A study of thermo-mechanical stress and its impact on through-silicon vias," J. Micromech.Microeng., vol. 18, no. 7, p. 075018, Jul. 2008.
8. X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. Tummala, and S. Sitaraman, "Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV)," in Proc. ECTC, 2009, pp. 624-629.
9. K. H. Lu, X. Zhang, S. K. Ryu, J. Im, R. Huang, and P. S. Ho, "Thermomechanical reliability of 3-D ICs containing through silicon vias," in Proc. ECTC, 2009, pp. 630-634.
10. S. E. Thompson, G. Sun, Y. Choi, and T. Nishida, "Uniaxial- processinduced strained-Si: Extending the CMOS roadmap," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.
11. A. P. Karmarker, X. Xu, and V.Moroz, "Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV)," in Proc. IEEE 47th Annu. IRPS, 2009, pp. 682-687.
12. J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," in Proc. ACM/IEEE DAC, 2010, pp. 803-806.
13. A. Mercha, G. Van der Plas, V. Moroz, I. De Wolf, P. Asimakopoulos, N. Minas, S. Domae, D. Perry, M. Choi, A. Redolfi, C. Okoro, Y. Yang, J. Van Olmen, S. Thangaraju, D. Sabuncuoglu Tezcan, P. Soussan, J. H. Cho, A. Yakovlev, P. Marchal, Y. Travaly, E. Beyne, S. Biesemans, and B. Swinnen, "Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance," in Proc. IEEE IEDM, 2010, pp. 2.2.1-2.2.4.
14. S. K. Ryu, K. H. Lu, X. Zhang, J. H. Im, P. S. Ho, and R. Huang, "Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects," IEEE Trans. Device Mater. Rel., vol. 11, no. 1, pp. 35-43, Mar. 2011.
15. L. B. Freund and S. Suresh, Thin Film Materials: Stress, Defect Formation, and Surface Evolution. Cambridge, U.K.: Cambridge Univ. Press, 2003.
16. A. Hamada, T. Furusawa, N. Saito, and E. Takeda, "A new aspect of mechanical stress effects in scaled MOS devices," IEEE Trans. Electron Devices, vol. 38, no. 4, pp. 895-900, Apr. 1991.
17. C.-L. Huang, H. R. Soleimani, G. J. Grula, J.W. Sleight, A. Villani, H. Ali, and D. A. Antoniadis, "LOCOS-induced stress effects on thin-film SOI devices," IEEE Trans. Electron Devices, vol. 44, no. 4, pp. 646-650, Apr. 1997. (Pubitemid 127764570)
18. A. T. Bradley, R. C. Jaeger, J. C. Suhling, and K. J. O'Connor, "Piezoresistive characteristics of short-channel MOSFETs on (100) silicon," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2009-2015, Sep. 2001. (Pubitemid 32922881)
19. C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, and R. Gwoziecki, "Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon," Solid State Electron., vol. 48, no. 4, pp. 561-566, 2004.
20. W. Zhao, J. He, R. E. Belford, L.-E. Wernersson, and A. Seabaugh, "Partially depleted SOI MOSFETs under uniaxial tensile strain," IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 317-323, Mar. 2004.
21. K. Uchida, R. Zednik, C.-H. Lu, H. Jagannathan, J. McVittie, P. C. McIntyre, and Y. Nishi, "Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs," in IEDM Tech. Dig., 2004, pp. 229-232. (Pubitemid 40940652)
22. C.-Y. Lu, H.-C. Lin, Y.-J. Lee, Y.-L. Shie, and C.-C. Chao, "Impacts of SiN-capping layer on the device characteristics and hot-carrier degradation of nMOSFETs," IEEE Trans. Device Mater. Rel., vol. 7, no. 1, pp. 175-180, Mar. 2007. (Pubitemid 47109517)
23. Y. Sun, S. Thompson, and T. Nishida, Strain Effect in Semiconductors: Theory and Device Applications. New York: Springer-Verlag, 2010.
24. S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.
25. D. R. Bland, "The associated flow rule of plasticity," J. Mech. Phys. Solids, vol. 6, no. 1, pp. 71-78, 1957.
26. Y. Xiang, X. Chen, and J. J. Vlassak, "The mechanical properties of electroplated Cu thin films measured by means of the bulge test technique," in Proc. Mat. Res. Soc. Symp., 2002, vol. 695, pp. L4.9.1-L4.9.6.
27. A. A. Volinsky, J. Vella, I. S. Adhihetty, V. Sarihan, L. Mercado, B. H. Yeung, and W. W. Gerberich, "Microstructure and mechanical properties of electroplated Cu thin films," in Proc. Mat. Res. Soc. Symp., 2001, vol. 649, pp. Q5.3.1-Q5.3.6.