Impact of buffer layer on atomic layer deposited TiAlO alloy dielectric quality for epitaxial-GaAs/Ge device application

IEEE Transactions on Electron Devices

Volumn 60, Issue 1, 2013, Pages 192-199

  Dalapati, G K ^a   Chia, C K ^a   Mahata, C ^b,c   Krishnamoorthy, S ^a   Tan, C C ^a   Tan, H R ^a   Maiti, Chinmay Kumar ^b   Chi, Dongzhi ^a  

^a INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING   (Singapore)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

^c Sungkyunkwan University   (South Korea)

Author keywords

Atomic layer deposition (ALD); epitaxial gallium arsenide (epi GaAs) MOS; TiAlO alloy high dielectric

Indexed keywords

ATOMIC LAYER DEPOSITED; DEVICE APPLICATION; ELECTRICAL CHARACTERISTIC; EPITAXIAL GALLIUM-ARSENIDE (EPI-GAAS) MOS; FLAT-BAND VOLTAGE; FREQUENCY DISPERSION; GE SUBSTRATES; HIGH-QUALITY INTERFACE; HIGH-SPEED TRANSISTORS; INTERFACE STATE DENSITY; METAL-OXIDE-SEMICONDUCTOR CAPACITORS; SHARP INTERFACE; SILICON PLATFORMS; SURFACE PASSIVATION; TIO;

ALUMINUM GALLIUM ARSENIDE; ATOMIC LAYER DEPOSITION; BUFFER LAYERS; DEPOSITS; ELECTRIC PROPERTIES; GALLIUM ALLOYS; GATE DIELECTRICS; GERMANIUM; OPTICAL WAVEGUIDES; SEMICONDUCTING GALLIUM; TITANIUM DIOXIDE;

GALLIUM ARSENIDE;

EID: 84871726812     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2226243     Document Type: Article

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