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Volumn 100, Issue 6, 2012, Pages

Atomic layer deposited (TiO 2) x(Al 2O 3) 1-x/In 0.53Ga 0.47As gate stacks for III-V based metal-oxide-semiconductor field-effect transistor applications

(14) Mahata, C a Mallik, S a Das, T a Maiti, C K a Dalapati, G K b Tan, C C b Chia, C K b Gao, H b Kumar, M K b Chiam, S Y b Tan, H R b Seng, H L b Chi, D Z b Miranda, E c

a INDIAN INSTITUTE OF TECHNOLOGY (India)

b INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING (Singapore)

c UNIVERSITAT AUTÒNOMA DE BARCELONA (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITED; CAPACITANCE VOLTAGE CHARACTERISTIC; CONDUCTION BAND OFFSET; GATE STACKS; HIGH-QUALITY INTERFACE; HYSTERESIS VOLTAGE; INTERFACE STATE DENSITY; LOW-FREQUENCY DISPERSIONS; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; NANOLAMINATE; OXIDATION STATE; POST DEPOSITION ANNEALING; TI-INCORPORATION; TIO;

ALUMINUM; ATOMIC FORCE MICROSCOPY; GATE DIELECTRICS; INDIUM; INTERFACES (MATERIALS); LOGIC GATES; MOSFET DEVICES; TITANIUM DIOXIDE; X RAY PHOTOELECTRON SPECTROSCOPY;

GALLIUM;

EID: 84857211987 PISSN: 00036951 EISSN: None Source Type: Journal
DOI: 10.1063/1.3684803 Document Type: Article

Times cited : (34)

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