String current in decananometer nand flash arrays: A compact-modeling investigation

IEEE Transactions on Electron Devices

Volumn 59, Issue 9, 2012, Pages 2331-2337

  Paolucci, Giovanni M ^a   Miccoli, Carmine ^a   Monzio Compagnoni, Christian ^a   Spinelli, Alessandro S ^a   Lacaita, Andrea L ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

Compact modeling; Flash memories; semiconductor device modeling; semiconductor device reliability

Indexed keywords

CHARGE TRAPPING/DETRAPPING; COMPACT MODELING; DAMAGE MECHANISM; DECA-NANOMETER; DRAIN-INDUCED BARRIER LOWERING; LOW FIELD MOBILITY; MOBILITY DEGRADATION; NAND FLASH; READ CURRENT; SATURATION LEVELS; SEMICONDUCTOR DEVICE RELIABILITY; VELOCITY SATURATION; VOLTAGE CHARACTERISTICS;

DEGRADATION; DRAIN CURRENT; FLASH MEMORY; INTERFACE STATES; SEMICONDUCTOR DEVICE MODELS;

CURRENT VOLTAGE CHARACTERISTICS;

EID: 84865451542     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2204060     Document Type: Article

References (28)

1. J. Hwang, J. Seo, Y. Lee, S. Park, J. Leem, J. Kim, T. Hong, S. Jeong, K. Lee, H. Heo, H. Lee, P. Jang, K. Park, M. Lee, S. Baik, J. Kim, H. Kkang, M. Jang, J. Lee, G. Cho, J. Lee, B. Lee, H. Jang, S. Park, J. Kim, S. Lee, S. Aritome, S. Hong, and S. Park, "A middle-1x nm NAND Flash memory cell (M1X-NAND) with highly manufacturable integration technologies," in IEDM Tech. Dig., 2011, pp. 199-202.
2. K. Prall and K. Parat, "25 nm 64 Gb MLC NAND technology and scaling challenges," in IEDM Tech. Dig., 2010, pp. 102-105.
3. J.-D. Lee, S.-H. Hur, and J.-D. Choi, "Effects of floating-gate interference on NAND Flash memory cell operation," IEEE Electron Device Lett., vol. 23, no. 5, pp. 264-266, May 2002. (Pubitemid 34630852)
4. A. Ghetti, L. Bortesi, and L. Vendrame, "3D simulation study of gate coupling and gate cross-interference in advanced floating gate nonvolatile memories," Solid State Electron., vol. 49, no. 11, pp. 1805-1812, Nov. 2005. (Pubitemid 41690866)
5. M. Park, K. Kim, J.-H. Park, and J.-H. Choi, "Direct field effect of neighboring cell transistor on cell-To-cell interference of NAND Flash cell arrays," IEEE Electron Device Lett., vol. 30, no. 2, pp. 174-177, Feb. 2009.
6. Y. S. Kim, D. J. Lee, C. K. Lee, H. K. Choi, S. S. Kim, J. H. Song, D. H. Song, J.-H. Choi, K.-D. Suh, and C. Chung, "New scaling limitation of the floating gate cell in NAND Flash memory," in Proc. IRPS, 2010, pp. 599-603.
7. C. Monzio Compagnoni, A. Ghetti, M. Ghidotti, A. S. Spinelli, and A. Visconti, "Data retention and program/erase sensitivity to the array background pattern in deca-nanometer NAND Flash memories," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 321-327, Jan. 2010.
8. S.-M. Joe, J.-H. Yi, S.-K. Park, H.-I. Kwon, and J.-H. Lee, "Positiondependent threshold-voltage variation by random telegraph noise in NAND Flash memory strings," IEEE Electron Device Lett., vol. 31, no. 7, pp. 635-637, Jul. 2010.
9. B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, "BSIM: Berkeley short-channel IGFET model for MOS transistors," IEEE J. Solid-State Circuits, vol. SSC-22, no. 4, pp. 558-566, Aug. 1987.
10. L. Larcher, A. Padovani, P. Pavan, P. Fantini, A. Calderoni, A. Mauri, and A. Benvenuti, "Modeling NAND Flash memories for IC design," IEEE Electron Device Lett., vol. 29, no. 10, pp. 1152-1154, Oct. 2008.
11. A. Spessot, C. Monzio Compagnoni, F. Farina, A. Calderoni, A. S. Spinelli, and P. Fantini, "Compact modeling of variability effects in nanoscale NAND flash memories," IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2302-2309, Aug. 2011.
12. W. Liu, X. Jin, J. Chen, M.-C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. K. Ko, and C. Hu, "BSIM3v3.2 MOSFET model users' manual," EECS Dept., Univ. California, Berkeley, CA, Tech. Rep. UCB/ERL M98/51, 1998.
13. G. M. Paolucci, C. Miccoli, C. Monzio Compagnoni, L. Crespi, A. S. Spinelli, and A. L. Lacaita, "Investigation of cycling-induced VT instabilities in NAND Flash cells via compact modeling," in Proc. IMW, Milano, Italy, 2012, pp. 194-197.
14. J.-D. Lee, C.-K. Lee, M.-W. Lee, H.-S. Kim, K.-C. Park, and W.-S. Lee, "A new programming disturbance phenomenon in NAND Flash memory by source/drain hot-electrons generated by GIDL current," in Proc. Non- Volatile Semicond. Memory Workshop, 2006, pp. 31-33. (Pubitemid 44753341)
15. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2009.
16. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
17. K. Chen, H. C. Wann, J. Dunster, P. K. Ko, C. Hu, and M. Yoshida, "MOSFET carrier mobility model based on gate oxide thickness threshold and gate voltages," Solid State Electron., vol. 39, no. 10, pp. 1515-1518, Oct. 1996. (Pubitemid 126364664)
18. A. Cros, K. Romanjek, D. Fleury, S. Harrison, R. Cerutti, P. Coronel, B. Dumont, A. Pouydebasque, R. Wacquez, B. Duriez, R. Gwoziecki, F. Boeuf, H. Brut, G. Ghibaudo, and T. Skotnicki, "Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling," in IEDM Tech. Dig., Dec. 2006, pp. 1-4.
19. G. Bidal, D. Fleury, G. Ghibaudo, F. Boeuf, and T. Skotnicki, "Guidelines for MOSFET device optimization accounting for L-dependent mobility degradation," in Proc. IEEE Silicon Nanoelectronics Workshop, Jun. 2009, pp. 5-6.
20. R. Yamada, Y.Mori, Y. Okuyama, J. Yugami, T. Nishimoto, and H. Kume, "Analysis of detrap current due to oxide traps to improve Flash memory retention," in Proc. IRPS, 2000, pp. 200-204.
21. J.-D. Lee, J.-H. Choi, D. Park, and K. Kim, "Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND Flash memory cells," in Proc. IRPS, 2003, pp. 497-501.
22. J.-D. Lee, J.-H. Choi, D. Park, and K. Kim, "Effects of interface trap generation and annihilation on the data retention characteristics of Flash memory cells," IEEE Trans. Device Mater. Rel., vol. 4, no. 1, pp. 110-117, Mar. 2004.
23. N. Mielke, H. Belgal, I. Kalastirsky, P. Kalavade, A. Kurtz, Q. Meng, N. Righos, and J. Wu, "Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling," IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 335-344, Sep. 2004.
24. N. Mielke, H. Belgal, A. Fazio, Q. Meng, and N. Righos, "Recovery effects in the distributed cycling of Flash memories," in Proc. IRPS, 2006, pp. 29-35. (Pubitemid 46964487)
25. M. Park, K. Suh, K. Kim, S.-H. Hur, K. Kim, and W.-S. Lee, "The effect of trapped charge distributions on data retention characteristics of NAND Flash memory cells," IEEE Electron Device Lett., vol. 28, no. 8, pp. 750- 752, Aug. 2007. (Pubitemid 47242040)
26. C. Monzio Compagnoni, C. Miccoli, R. Mottadelli, S. Beltrami, M. Ghidotti, A. L. Lacaita, A. S. Spinelli, and A. Visconti, "Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays," in Proc. IRPS, 2010, pp. 604-610.
27. C. Miccoli, C. Monzio Compagnoni, S. Beltrami, A. S. Spinelli, and A. Visconti, "Threshold-voltage instability due to damage recovery in nanoscale NAND Flash memories," IEEE Trans. Electron Devices, vol. 58, pp. 2406-2414, Aug. 2011.
28. H. Yang, H. Kim, S.-I. Park, J. Kim, S.-H. Lee, J.-K. Choi, D. Hwang, C. Kim, M. Park, K.-H. Lee, Y.-K. Park, J. K. Shin, and J.-T. Kong, "Reliability issues and models of sub-90 nm NAND Flash memory cells," in Proc. ICSICT, Oct. 2006, pp. 760-762.