Modeling nand flash memories for IC design

IEEE Electron Device Letters

Volumn 29, Issue 10, 2008, Pages 1152-1154

  Larcher, Luca ^a   Padovani, Andrea ^a   Pavan, Paolo ^a   Fantini, Paolo ^b   Calderoni, Alesandro ^b   Mauri, Aurelio ^b   Benvenuti, Augusto ^b  

^a UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^b Numonyx   (Italy)

Author keywords

Compact modeling; Flash memories; Semiconductor devices

Indexed keywords

CIRCUIT SIMULATION; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; NAND CIRCUITS; NETWORKS (CIRCUITS);

ACCURATE SIMULATION; CAPACITIVE COUPLING EFFECTS; COMPACT MODELING; COMPUTATIONAL EFFORTS; FLASH MEMORIES; FUTURE TECHNOLOGIES; IC DESIGNS; NAND FLASH MEMORIES; SEMICONDUCTOR DEVICES;

FLASH MEMORY;

EID: 54849374400     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2003179     Document Type: Article

References (6)

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2. M. Taub et al., "A 90 nm 512 Mb 166 MHz multilevel cell Flash memory with 1.5 MByte/s programming," in Proc. ISSCC Dig. Tech., 2005, pp. 54-56.
3. J.-D. Lee et al., "Effects of floating-gate interference on NAND Flash memory cell operation," IEEE Electron Device Lett., vol. 23, no. 5, pp. 264-266, May 2002.
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6. [Online]. Available: http://www-device.eecs.berkeley.edu/~bsim3/ arch_ftp.html