Data retention and program/erase sensitivity to the array background pattern in deca-nanometer NAND flash memories

IEEE Transactions on Electron Devices

Volumn 57, Issue 1, 2010, Pages 321-327

  Compagnoni Monzio, Christian ^a,b   Ghetti, Andrea ^c   Ghidotti, Michele ^a,b   Spinelli, Alessandro S ^a,b,d   Visconti, Angelo ^c  

^a POLITECNICO DI MILANO   (Italy)

^b Italian University Nano Electronics Team IUNET   (Italy)

^c Technology Development   (Italy)

^d IFN CNR   (Italy)

Author keywords

Electrostatic interference; Flash memories; Fowler Nordheim tunneling; Semiconductor device modeling

Indexed keywords

ACTIVE AREA; BIT-LINE ANDS; CROSSTALK EFFECT; DATA RETENTION; DECA-NANOMETER; ELECTRIC FIELD PROFILES; ELECTROSTATIC INTERFERENCE; FLOATING GATES; FOWLER-NORDHEIM TUNNELING; LOW THRESHOLD VOLTAGE; NAND FLASH MEMORY; NEGATIVE POTENTIAL; PROGRAM/ERASE; SEMICONDUCTOR DEVICE MODELING; TCAD SIMULATION; TUNNELING CURRENT; VOLTAGE LOSS;

CYTOLOGY; ELECTRIC FIELDS; FLASH MEMORY; NAND CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR SWITCHES; THREE DIMENSIONAL; THRESHOLD VOLTAGE; TUNNELING (EXCAVATION); WIND TUNNELS;

CELLS;

EID: 73349136258     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2035536     Document Type: Article

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